PSD813F1A-12J STMICROELECTRONICS [STMicroelectronics], PSD813F1A-12J Datasheet - Page 36
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PSD813F1A-12J
Manufacturer Part Number
PSD813F1A-12J
Description
Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
1.PSD813F1A-12J.pdf
(110 pages)
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PSD813F1
DECODE PLD (DPLD)
The DPLD, shown in Figure 16, is used for decod-
ing the address for internal and external compo-
nents. The DPLD can be used to generate the
following decode signals:
Figure 16. DPLD Logic Array
Note: 1. The address inputs are A19-A4 in 80C51XA mode.
36/110
MCELLAB.FB [7:0] (FEEDBACKS)
MCELLBC.FB [7:0] (FEEDBACKS)
PGR0 - PGR7
I /O PORTS (PORT A,B,C)
A [ 15:0 ]
PD [ 2:0 ] (ALE,CLKIN,CSI)
PDN (APD OUTPUT)
CNTRL [ 2:0 ] ( READ/WRITE CONTROL SIGNALS)
RESET
RD_BSY
8 sector selects for the main Flash memory
(three product terms each)
4 sector selects for the EEPROM (three
product terms each)
(1)
(INPUTS)
(24)
(16)
(8)
(8)
(8)
(3)
(3)
(1)
(1)
(1)
1 internal SRAM select signal (two product
terms)
1 internal CSIOP (PSD configuration register)
select signal
1 JTAG select signal (enables JTAG on Port
C)
2 internal peripheral select signals (peripheral
I/O mode).
3
3
3
3
3
3
3
3
3
3
3
3
2
1
1
1
1
RS0
CSIOP
PSEL0
PSEL1
JTAGSEL
EES 0
EES 1
EES 2
EES 3
FS0
FS1
FS7
FS2
FS3
FS5
FS6
FS4
SRAM SELECT
PERIPHERAL I/O
MODE SELECT
I/O DECODER
SELECT
8 FLASH MEMORY
SECTOR SELECTS
EEPROM
SELECTS
AI09226
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