HYB18L256169BF QIMONDA [Qimonda AG], HYB18L256169BF Datasheet - Page 24

• Manufacturer Part Number: HYB18L256169BF
• Description: 256-Mbit Mobile-RAM
• Manufacturer: QIMONDA [Qimonda AG]

2.4.6
Figure 23
Figure 24
During WRITE bursts, the first valid data-in element is registered coincident with the WRITE command, and
subsequent data elements are registered on each successive positive edge of CLK. Upon completion of a burst,
assuming no other commands have been initiated, the DQs remain in High-Z state, and any additional input data
is ignored.
Figure 25
Data Sheet
and
WRITE
WRITE Command
Basic WRITE Timing Parameters for DQs
Figure 26
show a single WRITE burst for each supported CAS latency setting.
24
WRITE bursts are initiated with a WRITE command, as
shown in
shown in
The starting column and bank addresses are provided
with the WRITE command, and Auto Precharge is
either enabled or disabled for that access. If Auto
Precharge is enabled, the row being accessed is
precharged at the completion of the write burst. For the
generic WRITE commands used in the following
illustrations, Auto Precharge is disabled.
Figure
Figure
24; they apply to all write operations.
23. Basic timings for the DQs are
HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Functional Description
02032006-MP0M-7FQG
Rev. 1.02, 2006-12