HYB18L256169BF QIMONDA [Qimonda AG], HYB18L256169BF Datasheet - Page 8

• Manufacturer Part Number: HYB18L256169BF
• Description: 256-Mbit Mobile-RAM
• Manufacturer: QIMONDA [Qimonda AG]

1. At first, device core power (V
2. After V
3. Wait for 200µs while issuing NOP or DESELECT commands.
4. Issue a PRECHARGE ALL command, followed by NOP or DESELECT commands for at least t
5. Issue two AUTO REFRESH commands, each followed by NOP or DESELECT commands for at least t
6. Issue two MODE REGISTER SET commands for programming the Mode Register and Extended Mode
Following these steps, the Mobile-RAM is ready for normal operation.
2.2
2.2.1
The Mode Register is used to define the specific mode of operation of the Mobile-RAM. This definition includes
the selection of a burst length (bits A0-A2), a burst type (bit A3), a CAS latency (bits A4-A6), and a write burst
mode (bit A9). The Mode Register is programmed via the MODE REGISTER SET command (with BA0 = 0 and
BA1 = 0) and will retain the stored information until it is programmed again or the device loses power.
The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before
initiating any subsequent operation. Violating either of these requirements results in unspecified operation.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
MR
Mode Register Definition
Field
WB
CL
BT
Data Sheet
BA1
0
and V
Assert and hold CKE and DQM to a HIGH level.
period.
Register, each followed by NOP or DESELECT commands for at least t
registers are programmed is not important. Programming of the Extended Mode Register may be omitted when
default values (half drive strength, 4 bank refresh) will be used.
Bits
9
[6:4]
3
BA0
DDQ
DD
0
Register Definition
Mode Register
and V
are driven from a single power converter output.
Type Description
w
w
w
A12
0
DDQ
are stable and CKE is HIGH, apply stable clocks.
Write Burst Mode
0
1
CAS Latency
010 2
011 3
Note: All other bit combinations are RESERVED.
Burst Type
0
1
A11
0
Burst Write
Single Write
Sequential
Interleaved
DD
A10
0
) and device IO power (V
WB
A9
A8
0
(BA[1:0] = 00
A7
8
0
DDQ
) must be brought up simultaneously. Typically V
B
A6
)
CL
A5
MRD
A4
period; the order in which both
HY[B/E]18L256169BF-7.5
BT
256-Mbit Mobile-RAM
A3
Functional Description
02032006-MP0M-7FQG
A2
Rev. 1.02, 2006-12
RP
BL
A1
period.
RC
A0
DD