HYB18T512400BF-2.5 QIMONDA [Qimonda AG], HYB18T512400BF-2.5 Datasheet - Page 3

• Manufacturer Part Number: HYB18T512400BF-2.5
• Description: 512-Mbit Double-Data-Rate-Two SDRAM
• Manufacturer: QIMONDA [Qimonda AG]

1
This chapter gives an overview of the 512-Mbit Double-Data-Rate-Two SDRAM product family and describes its main
characteristics.
1.1
The 512-Mbit Double-Data-Rate-Two SDRAM offers the following key features:
• 1.8 V
• DRAM organizations with 4 and 8 data in/outputs
• Double-Data-Rate-Two architecture: two data transfers
• Programmable CAS Latency: 3, 4, 5 and 6
• Programmable Burst Length: 4 and 8
• Differential clock inputs (CK and CK)
• Bi-directional, differential data strobes (DQS and DQS) are
• DLL aligns DQ and DQS transitions with clock
• DQS can be disabled for single-ended data strobe
• Commands entered on each positive clock edge, data and
• Data masks (DM) for write data
• Posted CAS by programmable additive latency for better
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
Rev. 1.1, 2007-05
03292006-YBYM-WG0Z
Product Type Speed Code
Speed Grade
Max. Clock Frequency
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
1.8 V
per clock cycle four internal banks for concurrent operation
transmitted / received with data. Edge aligned with read
data and center-aligned with write data.
operation
data mask are referenced to both edges of DQS
command and data bus efficiency
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
±
±
0.1 V Power Supply
0.1 V (SSTL_18) compatible I/O
Overview
Features
@CL6
@CL5
@CL4
@CL3
f
f
f
f
t
t
t
t
CK6
CK5
CK4
CK3
RCD
RP
RAS
RC
–25F
DDR2–800D 5–5–5
400
400
266
200
12.5
12.5
45
57.5
3
• Off-Chip-Driver impedance adjustment (OCD) and On-
• Auto-Precharge operation for read and write bursts
• Auto-Refresh, Self-Refresh and power saving Power-
• Average Refresh Period 7.8 µs at a
• Programmable self refresh rate via EMRS2 setting
• Programmable partial array refresh via EMRS2 settings
• DCC enabling via EMRS2 setting
• Full and reduced Strength Data-Output Drivers
• 1kB page size for ×4 & ×8, 2kB page size for ×16
• Package: P(G)-TFBGA-60 and P(G)-TFBGA-84
• RoHS Compliant Products
• All Speed grades faster than DDR2–400 comply with
Die-Termination (ODT) for better signal quality
Down modes
85 °C, 3.9 µs between 85 °C and 95 °C
DDR2–400 timing specifications when run at a clock rate
of 200 MHz.
512-Mbit Double-Data-Rate-Two SDRAM
Performance Table for –25F and –2.5
DDR2–800E 6–6–6
400
333
266
200
15
15
45
60
–2.5
HYB18T512[40/80/16]0B[C/F]
1)
Internet Data Sheet
T
CASE
lower than
TABLE 1
Unit
—
MHz
MHz
MHz
MHz
ns
ns
ns
ns