HYB18T512400BF-2.5 QIMONDA [Qimonda AG], HYB18T512400BF-2.5 Datasheet - Page 42

• Manufacturer Part Number: HYB18T512400BF-2.5
• Description: 512-Mbit Double-Data-Rate-Two SDRAM
• Manufacturer: QIMONDA [Qimonda AG]

3) Inputs are not recognized as valid until
4) The output timing reference voltage level is
5)
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
3) Inputs are not recognized as valid until V
4) The output timing reference voltage level is V
5) t
Rev. 1.1, 2007-05
03292006-YBYM-WG0Z
Speed Grade
QAG Sort Name
CAS-RCD-RP latencies
Parameter
Clock Frequency
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
t
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0).
input reference level is the crosspoint when in differential strobe mode.
RAS.MAX
RAS.MAX
is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x
is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x t
@ CL = 3
@ CL = 4
@ CL = 5
V
REF
REF
V
stabilizes. During the period before
stabilizes. During the period before V
TT
TT
.
. See section 8 for the reference load for timing measurements.
Symbol
t
t
t
t
t
t
t
CK
CK
CK
RAS
RC
RCD
RP
42
Speed Grade Definition Speed Bins for DDR2-400B
DDR2–400B
–5
3–3–3
Min.
5
5
5
40
55
15
15
V
REF
REF
512-Mbit Double-Data-Rate-Two SDRAM
stabilizes, CKE = 0.2 x
stabilizes, CKE = 0.2 x V
Max.
8
8
8
70000
—
—
—
HYB18T512[40/80/16]0B[C/F]
Unit
t
—
ns
ns
ns
ns
ns
ns
ns
CK
V
DDQ
DDQ
Internet Data Sheet
is recognized as low.
is recognized as low.
TABLE 46
Note
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
t
REFI
REFI
.
.