HYB18T512400BF-2.5 QIMONDA [Qimonda AG], HYB18T512400BF-2.5 Datasheet - Page 53

• Manufacturer Part Number: HYB18T512400BF-2.5
• Description: 512-Mbit Double-Data-Rate-Two SDRAM
• Manufacturer: QIMONDA [Qimonda AG]

13) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C
14) 0 °C ≤
15) 85 °C <
16) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
17) The
18) The maximum limit for the
19) Minimum
20) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active power-
21) WR must be programmed to fulfill the minimum requirement for the
Rev. 1.1, 2007-05
03292006-YBYM-WG0Z
Parameter
DQ output access time from CK / CK
CAS A to CAS B command period
CK, CK high-level width
CKE minimum high and low pulse width
CK, CK low-level width
Auto-Precharge write recovery + precharge
time
Minimum time clocks remain ON after CKE
asynchronously drops LOW
DQ and DM input hold time (differential data
strobe)
DQ and DM input hold time (single ended data
strobe)
DQ and DM input pulse width (each input)
DQS output access time from CK / CK
DQS input low (high) pulse width (write cycle)
DQS-DQ skew (for DQS & associated DQ
signals)
Write command to 1st DQS latching transition
DQ and DM input setup time (differential data
strobe)
DQ and DM input setup time (single ended
data strobe)
DQS falling edge hold time from CK (write
cycle)
DQS falling edge to CK setup time (write cycle)
and 95 °C.
Products (RoHS Compliant)” on Page
performance (bus turnaround) degrades accordingly.
down mode” (MR, A12 = “0”) a fast power-down exit timing
power-down exit timing
up to the next integer value.
refers to the application clock period. WR refers to the WR parameter stored in the MRS.
t
RRD
T
T
CASE
timing parameter depends on the page size of the DRAM organization. See
CASE
t
WTR
≤ 85 °C
≤ 95 °C
is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
t
XARDS
t
WPST
t
DAL
has to be satisfied.
parameter is not a device limit. The device operates with a greater value for this parameter, but system
= WR + (
6.
t
RP
/
t
CK
DRAM Component Timing Parameter by Speed Grade - DDR2-400
). For each of the terms, if not already an integer, round to the next highest integer.
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AC
CCD
CH
CKE
CL
DAL
DELAY
DH
DH1
DIPW
DQSCK
DQSL,H
DQSQ
DQSS
DS
DS1
DSH
DSS
(base)
(base)
(base)
(base)
t
XARD
53
can be used. In “low active power-down mode” (MR, A12 =”1”) a slow
t
WR
DDR2–400
–600
2
0.45
3
0.45
WR +
t
275
–25
0.35
–500
0.35
—
–0.25
150
–25
0.2
0.2
Min.
IS
timing parameter, where
+
t
CK
t
RP
+
t
IH
512-Mbit Double-Data-Rate-Two SDRAM
Table 5 “Ordering Information for Lead-Free
Max.
+600
—
0.55
—
0.55
—
—
—
—
—
+500
—
350
+0.25
—
—
—
—
WR
HYB18T512[40/80/16]0B[C/F]
MIN
[cycles] =
Unit
ps
t
t
t
t
t
ns
ps
ps
t
ps
t
ps
t
ps
ps
t
t
Internet Data Sheet
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
t
WR
(ns)/
TABLE 50
t
Note
1)2)3)4)5)6)
7)20)
8)
9)
10)
10)
10)
10)
CK
(ns) rounded
t
CK