HYB18T512400BF-2.5 QIMONDA [Qimonda AG], HYB18T512400BF-2.5 Datasheet - Page 59

• Manufacturer Part Number: HYB18T512400BF-2.5
• Description: 512-Mbit Double-Data-Rate-Two SDRAM
• Manufacturer: QIMONDA [Qimonda AG]

7.4
This chapter describes the ODT AC electrical characteristics.
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
1) New units, “t
2) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
3) ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Rev. 1.1, 2007-05
03292006-YBYM-WG0Z
Symbol
t
t
t
t
t
t
t
t
Symbol
t
t
t
t
t
t
t
t
AOND
AON
AONPD
AOFD
AOF
AOFPD
ANPD
AXPD
AOND
AON
AONPD
AOFD
AOF
AOFPD
ANPD
AXPD
the ODT resistance is fully on. Both are measured from
10 ns (= 2 x 5 ns) after the clock edge that registered a first ODT HIGH if
Both are measured from
12.5 ns (= 2.5 x 5 ns) after the clock edge that registered a first ODT HIGH if
under operation. Unit “
DDR2-533, “
be registered at
the ODT resistance is fully on. Both are measured from
2 clock cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges.
Both are measured from
(= 0.5 x 3 ns) after the second trailing clock edge counting from the clock edge that registered a first ODT LOW and by counting the actual
input clock edges.
Parameter / Condition
ODT turn-on delay
ODT turn-on
ODT turn-on (Power-Down Modes)
ODT turn-off delay
ODT turn-off
ODT turn-off (Power-Down Modes)
ODT to Power Down Mode Entry Latency
ODT Power Down Exit Latency
Parameter / Condition
ODT turn-on delay
ODT turn-on
ODT turn-on (Power-Down Modes)
ODT turn-off delay
ODT turn-off
ODT turn-off (Power-Down Modes)
ODT to Power Down Mode Entry Latency
ODT Power Down Exit Latency
CK.AVG
t
CK
” is used for both concepts. Example:
T
m
” and “
+ 2, even if (
ODT AC Electrical Characteristics
n
CK
t
t
n
AOFD
AOFD
” represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and
CK
”, are introduced in DDR2-667 and DDR2-800. Unit “
ODT AC Characteristics and Operating Conditions for DDR2-533 and DDR2-400
ODT AC Characteristics and Operating Conditions for DDR2-667 and DDR2-800
, which is interpreted differently per speed bin. For DDR2-667/800, if
. Both are measured from
T
m
+ 2 -
T
m
) is 2 x
t
CK.AVG
t
XP
t
t
= 2 [
t
AOND
AOND
AOFD
+
t
n
ERR.2PER(Min)
, which is interpreted differently per speed bin. For DDR2-400/533,
, which is interpreted differently per speed bin. For DDR2-667/800,
, which is interpreted differently per speed bin. For DDR2-400/533,
CK
Values
Min.
2
t
t
2.5
t
t
3
8
Values
Min.
2
t
t
2.5
t
t
3
8
] means; if Power Down exit is registered at
AC.MIN
AC.MIN
AC.MIN
AC.MIN
AC.MIN
AC.MIN
AC.MIN
AC.MIN
59
+ 2 ns
+ 2 ns
+ 2 ns
+ 2 ns
.
t
CK
= 5 ns.
t
CK
= 5 ns.
t
CK.AVG
Max.
2
t
2
2.5
t
2.5
—
—
Max.
2
t
2
2.5
t
2.5
—
—
AC.MAX
AC.MAX
AC.MAX
AC.MAX
512-Mbit Double-Data-Rate-Two SDRAM
t
t
CK +
CK +
t
t
” represents the actual
CK +
CK +
t
t
+ 1 ns
AC.MAX
+ 0.6 ns
+ 0.7 ns
AC.MAX
+ 0.6 ns
t
t
AC.MAX
AC.MAX
t
CK(avg)
+ 1 ns
+ 1 ns
HYB18T512[40/80/16]0B[C/F]
+ 1 ns
+ 1 ns
= 3 ns is assumed,
T
m
, an Active command may
t
CK.AVG
Unit
t
ns
ns
t
ns
ns
t
t
Unit
n
ns
ns
n
ns
ns
n
n
Internet Data Sheet
CK
CK
CK
CK
CK
CK
CK
CK
TABLE 54
TABLE 55
of the input clock
t
AOFD
Note
1)
2)
Note
1)
1)2)
1)
1)
1)3)
1)
1)
1)
is 1.5 ns
t
t
t
AOND
AOND
AOFD
is
is
is