STC4130-I ETC2 [List of Unclassifed Manufacturers], STC4130-I Datasheet - Page 14

• Manufacturer Part Number: STC4130-I
• Description: Synchronous Clock for SETS
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

0x45-0x48).
On either transition, from Synchronized to Holdover,
or back from Holdover to Synchronized, an applica-
tion programmable maximum slew rate of 1, 1.5, or 2
ppm/second (or no slew rate limit) is applied, as writ-
ten to the T(0/4)_HO_Ramp registers (0x30/ 0x4d).
Output Clocks
The clock output section includes 4 clock genera-
tions, an APLL, and four dividers, and generates nine
synchronized clocks, as shown in figure 5.
The first synthesizer drives an analog PLL and gen-
erates five output clocks. It is driven from the T0
DPLL:
T0 DPLL
T4 DPLL
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CLK0: 155.52 MHz (LVPECL), enabled/dis-
abled by writing the CLK0_Sel register
(0x56), bit 0.
CLK1: Programmable at 19.44MHz,
38.88MHz, 77.76 MHz, and “disabled”, by
writing to the CLK1_Sel register (0x57), bits
0 - 1.
CLK2: Programmable at 19.44MHz,
38.88MHz, 77.76 MHz, and “disabled”, by
writing to the CLK2_Sel register (0x58), bits
0 - 1.
CLK3: 8kHz, 50% duty cycle or programma-
ble pulse width, and may be disabled by writ-
ing to the CLK3_Sel register (0x59), bits 0 -
5.
CLK4: 2kHz, 50% duty cycle or programma-
Generation
Clk
Figure 5: Output Clocks
APLL
© Copyright 2006 The Connor-Winfield Corp.
Generation
Generation
Generation
Clk
Clk
Clk
Divider
Divider
Divider
Divider
Clk4
Clk6
Clk7
Clk0
Clk1
Clk3
Clk5
Data Sheet #: TM084
Clk2
155.52 MHz
19.44 / 38.88 /
77.76 MHz
19.44 / 38.88 /
77.76 MHz
2 KHz
8 KHz
DS3, E3
nxDS1, nxE1
n = 1,2,4,8,16
T1, E1
Two synthesizers generate additional clocks from the
T0 clock generator:
One synthesizer is driven by the T4 clock generator:
When a clock output is disabled, the pin is tri-stated.
In
T4_Xsync_OUT outputs provide phase information
and state data for master/slave operation of the T0
and T4 clock generators.
Note that the CLK1, 2, 5 and 6 are phase aligned
with the CLK3 (8KHz) as shown in Figure 7. CLk3 is
phase aligned with CLK4 (2KHz).
All Rights Reserved
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addition,
Page 14 of 44
ble pulse width, and may be disabled by writ-
ing to the CLK4_Sel register (0x5a), bits 0 -
5.
CLK5: Either DS3 or E3 rate, or “disabled”,
programmed by writing to the CLK5_Sel reg-
ister (0x5b), bits 0 - 1.
CLK6: Programmable at nxDS1 or nxE1
where n=1,2,4,8,16, or may be disabled, by
writing to the CLK6_Sel register (0x5c), bits
0 - 3.
CLK7: Either DS1 or E1 rate, or “disabled”,
programmed by writing to the CLK7_Sel reg-
ister (0x5d), bits 0 - 1.
Synchronous Clock for SETS
Specifications subject to change without notice
the
Rev: P02
T0_Xsync_OUT
STC4130
Data Sheet
Date: 12/5/06
and