STC4130-I ETC2 [List of Unclassifed Manufacturers], STC4130-I Datasheet - Page 38

• Manufacturer Part Number: STC4130-I
• Description: Synchronous Clock for SETS
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

CLK2_Sel, 0x58 (R/W)
Selects or disables the CLK2 output.
Default value: 2.
CLK3_Sel, 0x59 (R/W)
Selects or disables the CLK3 output, and sets the pulse width. In variable pulse width, the width may be
selected from 1 to 62 times the period of the 155.52MHz output (~6.43nS to 399nS).
Default value: 63.
CLK4_Sel, 0x5a (R/W)
Selects or disables the CLK4 output, and sets the pulse width. In variable pulse width, the width may be
selected from 1 to 62 times the period of the 155.52MHz output (~6.43nS to 399nS).
Default value: 63.
CLK5_Sel, 0x5b (R/W)
Selects or disables the CLK5 output.
Address
Address
Address
Address
0x58
0x59
0x5a
0x5b
Bit7
Bit7
Bit7
Bit7
Not used
Not used
© Copyright 2006 The Connor-Winfield Corp.
0x59, bits 5 ~ 0
0x5a, bits 5 ~ 0
Bit6
Bit6
Bit6
Bit6
1 ~ 62
1 ~ 62
63
63
0
0
Data Sheet #: TM084
0x58, bits 1 ~ 0
0x5b, bits 1 ~ 0
Bit5
Bit5
Bit5
Bit5
Not used
Not used
0
1
2
3
0
Pulse width 1 to 62 cycles of 155.52MHz
Pulse width 1 to 62 cycles of 155.52MHz
Bit4
Bit4
Bit4
Bit4
CLK3 8KHz output
CLK4 2KHz output
50% duty cycle
50% duty cycle
CLK2 output
CLK5 output
All Rights Reserved
19.44MHz
38.88MHz
77.76MHz
Disabled
Disabled
Disabled
Disabled
Page 38 of 44
Bit3
Bit3
Bit3
Bit3
Synchronous Clock for SETS
CLK3 Select
CLK4 Select
Specifications subject to change without notice
Bit2
Bit2
Bit2
Bit2
Rev: P02
STC4130
Data Sheet
Bit1
Bit1
Bit1
Bit1
CLK2 Select
CLK2 Select
Date: 12/5/06
Bit0
Bit0
Bit0
Bit0