STC4130-I ETC2 [List of Unclassifed Manufacturers], STC4130-I Datasheet - Page 40

• Manufacturer Part Number: STC4130-I
• Description: Synchronous Clock for SETS
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

Interrupt event, 0 = no event, 1 = event occurred. Interrupt 8 and 9 apply to the 12 reference inputs only.
Interrupts are cleared by writing “1’s” to the bit positions to be cleared (See General Register Operation,
Clearing bits in the Interrupt Status Register section).
Intr_Enable, 0x60 (R/W)
Interrupt disable/enable, 0 = disable, 1 = enable.
Default value: 0.
Application Notes
This section describes typical application use of the STC4130 device. The General section applies to all appli-
cation variations, while the remaining sections detail use depending on the level of control and automatic oper-
ation the application desires.
General
Power and Ground
Well-planned noise-minimizing power and ground are essential to achieving the best performance of the
device. The device requires 3.3 and 1.8V digital power and 1.8V analog power input. All digital I/O is at 3.3V,
LVTTL compatible. The 1.8V may originate from a common source but should be individually filtered and iso-
lated, as shown in Figure 17. Alternatively, a separate 1.8V regulator may be used for the analog 1.8 volts. R/C
filter components should be chosen for minimum inductance and kept as close to the chip as possible.
It is desirable to provide individual bypass capacitors, located close to the chip, for each of the digital power
input leads, subject to board space and layout constraints. On power-up, it is desirable to have the 1.8V either
lead or be coincident with, but not lag the application of 3.3V.
Digital ground should be provided by as continuous a ground plane as possible. While the analog and digital
grounds are tied together inside the chip, it is recommended that they be tied together externally at a single
point close to the chip as well.
Address
Address
0x60
0x61
0x5f
Enable
Intr 7
Bit7
Bit7
© Copyright 2006 The Connor-Winfield Corp.
Enable
Intr 6
Bit6
Bit6
Data Sheet #: TM084
Enable
Intr 5
Bit5
Bit5
Enable
Intr 4
Bit4
Bit4
All Rights Reserved
Page 40 of 44
Enable
Intr 3
Bit3
Bit3
Synchronous Clock for SETS
Specifications subject to change without notice
Enable
Intr 2
Bit2
Bit2
Rev: P02
STC4130
qualified to
Any refer-
changed
from dis-
Event 9:
qualified
Enable
Enable
Data Sheet
ence
Intr 1
Intr 9
Bit1
Bit1
Date: 12/5/06
from quali-
fied to dis-
Any refer-
changed
Event 8:
qualified
Enable
Enable
Intr 0
Intr 8
ence
Bit0
Bit0