STC4130-I ETC2 [List of Unclassifed Manufacturers], STC4130-I Datasheet - Page 21
STC4130-I
Manufacturer Part Number
STC4130-I
Description
Synchronous Clock for SETS
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
1.STC4130-I.pdf
(44 pages)
- Current page: 21 of 44
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Intel Bus
In Intel mode, the device will interface to 80x86 type processors. The BUS_CS, BUS_WRB, BUS_RDB,
BUS_A(6-0), BUS_AD(7-0), and BUS_RDY pins are used, corresponding to CS, WRB, RDB, A, AD, and RDY,
respectively. Timing is as follows:
WRB
RDB
CS
RDY
AD
A
Symbol
Symbol
t
t
t
t
t
RDYd2
RDYd1
t
RDBs
RDBh
RDB1
t
t
RDB
t
t
Dd1
Dd2
As
Ah
t
© Copyright 2006 The Connor-Winfield Corp.
As
t
RDYd1
RDY high-z delay after CS high
Read setup time
Read low time
Read hold time
Time between consecutive reads
Address setup
Address hold
Data valid delay from RDB high
Data high-z delay from RDB high
CS low to RDY high delay
t
RDBs
Table 8: Intel Bus Read Timing
Figure 13: Intel Bus Read Timing
Data Sheet #: TM084
t
RDYd2
t
Dd1
Description
Description
Address
t
RDY
t
RDB
Data
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Page 21 of 44
t
RDYh
t
RDB1
Synchronous Clock for SETS
Min
Min
40
50
10
0
0
0
t
t
Ah
Dd2
Specifications subject to change without notice
t
RDBh
Max
Max
50
10
13
7
t
RDYd3
Rev: P02
Unit
Unit
STC4130
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
Data Sheet
Date: 12/5/06
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