TSI-8 AGERE [Agere Systems], TSI-8 Datasheet - Page 15

• Manufacturer Part Number: TSI-8
• Description: 8K x 8K Time-Slot Interchanger
• Manufacturer: AGERE [Agere Systems]

Hardware Design Guide, Revision 1
November 2, 2005
Figure 6-3 shows the ac timing specifications for the
Table 6-3. CMOS Output ac Timing Specification *
* Test load = 50 pF (total).
Note: This figure assumes TSI-8 is programmed to sample FSYNC on rising edge of CHICLK.
Table 6-4. CHI Interface Timing
Agere Systems Inc.
* Applies if Driver_Enable_Control = 01. For Driver_Enable_Control = 11 refer to
Parameter
CHICLK
FSYNC
Parameter
RXD
TXD
t
t
t
t
t
t
t
13
14
15
16
17
18
19
t
t
10
9
FSYNC Setup Time to Active CHICLK Edge
FSYNC Hold Time from Active CHICLK Edge
RXD Setup to Active CHICLK Edge
RXD Hold Time from Active CHICLK Edge
TXD High Z to Data Valid
TXD Propagation Delay from Active CHICLK Edge
Transmit Data High Impedance*
t
t
13
15
Rise Time (20%—80%)
Fall Time (80%—20%)
t
17
t
t
14
16
Description
20%
t
18
Figure 6-3. ac Timing Specification
t9
Description
Figure 6-4. CHI Interface Timing
t
19
80 %
CMOS outputs
Min
—
—
Figure 6-15 CHI 3-State Output Control on page
on the device.
80 %
t10
Typ
1.5
1.5
8K x 8K Time-Slot Interchanger
20 %
Min
10
10
—
—
5
5
2
Max
7
7
Max
—
—
—
—
15
12
15
21.
Unit
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
TSI-8
15