TSI-8 AGERE [Agere Systems], TSI-8 Datasheet - Page 8

• Manufacturer Part Number: TSI-8
• Description: 8K x 8K Time-Slot Interchanger
• Manufacturer: AGERE [Agere Systems]

TSI-8
8K x 8K Time-Slot Interchanger
3.3 Ball Types
This table describes each type of input, output, and I/O ball used on the TSI-8.
Table 3-4. Ball Types
The dc switching and other electrical characteristics are specified later in this document.
3.4 Ball Definitions
This section describes the function of each of the device balls. The balls are listed by ball name. Package ball numbers are
listed in
put, output, etc.) are described in
Table 3-5. Timing Port
Table 3-6. Transmit and Receive Concentration Highways
8 8
RXD[31:00] I pd Receive Data [31:00]. Receive concentration highways. These are serial, synchronous data streams
TXD[31:00] I/O Transmit Data [31:00]. Normally these are output concentration highway data streams with data rate
Ball Name Type
Ball Name Type
CKSPD0
CKSPD1
CHICLK
FSYNC
Type Label
None
O od
I pd
I pu
I/O
Table 3-1
O
P
I
I pd Clock Speed. Reserved, leave disconnected. 20 kΩ pull-down resistor.
I
I
I
of this document. The static parameters (drive currents, switching thresholds, etc.) for each ball type (in-
CMOS input, TTL switching thresholds.
CMOS input, TTL switching thresholds with internal pull-down resistor.
CMOS input, TTL switching thresholds with internal pull-up resistor.
CMOS output.
Open drain output.
Bidirectional ball; CMOS input with TTL switching thresholds and CMOS output.
Analog inputs for external resistors, capacitors, voltage references, etc.
Power and ground.
which may be individually programmed to operate at 2.048 Mbits/s, 4.096 Mbits/s, 8.192 Mbits/s, or
16.384 Mbits/s. They carry 32, 64, 128, or 256 time slots (respectively) each occupying eight contiguous
bits. 20 kΩ pull-down resistor.
options identical to the RXD inputs. These balls can be configured to operate as bidirectional multiplex
ports such as H.110. Further information can be found in the system design guide. 20 kΩ resistor
connected to V
Frame Synchronization. This signal indicates the beginning of a 125 µs frame event (8 kHz). The
FSYNC ball can be programmed as active-low or active-high, but its polarity is the same for all concen-
tration highway interfaces (CHI). FSYNC can be sampled on either the positive or negative edge of
CHICLK. Time-slot numbers and bit offsets for each CHI are assigned relative to the detection of
FSYNC.
Clock. This is the master synchronous clock for the transmit and receive concentration highways. The
frequency can be 8.192 MHz or 16.384 MHz. It must be at least as fast as the highest CHI data rate.
Clock Speed. Static control input that should be tied according to the frequency of CHICLK. If CHICLK
is connected to an 8.192 MHz source, CKSPD0 should be tied to V
16.384 MHz source, CKSPD0 should be tied to V
Table 5-1
PRE
.
through
Table
5-4.
Name/Description
Name/Description
Description
DD33
.
Hardware Design Guide, Revision 1
SS
. If CHICLK is connected to a
November 2, 2005
Agere Systems Inc.