TSI-8 AGERE [Agere Systems], TSI-8 Datasheet - Page 16

• Manufacturer Part Number: TSI-8
• Description: 8K x 8K Time-Slot Interchanger
• Manufacturer: AGERE [Agere Systems]

TSI-8
8K x 8K Time-Slot Interchanger
All timing specifications also apply under the following conditions:
Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the CHICLK.
Notes:
1/4 bit offset not valid with 16 Mbits/s data.
For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and sampled by the rising edge of the CHICLK.
16
16
If FS is active-low.
If the falling edge of CHICLK is specified as the active edge.
At all RXD and TXD rates (16.384 Mbits/s, 8.192 Mbits/s, 4.096 Mbits/s, or 2.048 Mbits/s) with a CHICLK frequency of
16.384 MHz or 8.192 MHz.
FSYNC
CHICLK
w/ TS offset = 255,
FSYNC
CHICLK
w/ TS offset = 13,
w/ TS offset = 1,
w/ bit offset = 1
w/ 2¾ bit offset
w/ bit offset = 7
bit offset = 3¼
bit offset = 7¾
w/ ¼ bit offset
w/ ½ bit offset
w/ ¾ bit offset
w/ TS offset = 255,
bit offset = 0
w/ TS offset = 1,
w/ 0 offset
w/ bit offset = 1
Figure 6-5. Typical Receive CHI Timing with 16.384 Mbits/s Data and 16.384 MHz CHICLK
bit offset = 7½
w/ ½ bit offset
bit offset = 0
w/ 0 offset
Figure 6-6. Transmit CHI Timing with 16.384 Mbits/s Data and 16.384 MHz CHICLK
TS255 B5
TS255 B3
TS255 B6
TS255 B6
TS255 B5
TS254 B7
TS254 B6
TS255 B6
TS242 B3
TS255 B5
TS255 B4
TS254 B5
TS255 B6
TS255 B6
TS255 B4
TS255 B7
TS255 B5
TS255 B6
TS255 B7
TS255 B6
TS255 B0
TS254 B7
TS255 B7
TS242 B4
TS255 B6
TS255 B5
TS254 B6
TS255 B7
TS255 B7
TS255 B5
TS0 B0
TS255 B7
TS255 B1
TS255 B0
TS255 B6
TS255 B7
TS0 B0
TS242 B5
TS0 B0
data sampled
data sampled
data sampled
data sampled
TS0 B0
TS255 B7
TS255 B6
TS254 B7
TS255 B6
data sampled
data sampled
TS0 B0
TS0 B1
TS255 B1
TS255 B2
data sampled
TS0 B1
TS0 B0
TS255 B7
TS242 B6
TS0 B0
data sampled
data sampled
data sampled
TS0 B1
TS0 B1
TS255 B7
TS255 B7
TS255 B0
TS0 B1
TS0 B2
TS0 B0
TS255 B3
TS255 B2
TS0 B2
TS0 B1
TS242 B7
TS0 B2
TS0 B0
TS0 B1
TS0 B2
TS0 B2
TS0 B0
TS0 B3
TS255 B1
TS0 B1
TS0 B0
TS255 B4
TS255 B3
TS0 B3
TS0 B2
TS243 B0
TS0 B3
TS0 B1
TS0 B2
TS0 B3
TS0 B3
TS0 B1
TS0 B4
TS255 B5
TS255 B4
TS255 B2
Hardware Design Guide, Revision 1
TS0 B4
TS0 B3
TS0 B2
TS0 B1
TS243 B1
TS0 B4
TS0 B4
TS0 B2
TS0 B3
TS0 B4
TS0 B2
TS0 B5
TS255 B6
TS255 B5
TS0 B5
TS0 B4
TS255 B3
TS0 B3
TS0 B2
TS243 B2
TS0 B5
TS0 B5
TS0 B3
TS0 B4
TS0 B5
TS0 B3
TS0 B6
TS255 B7
TS255 B6
TS243 B3
TS255 B4
TS0 B4
TS0 B3
November 2, 2005
TS0 B7
TS0 B4
TS0 B5
TS255 B7
TS0 B 0
Agere Systems Inc.
TS243 B4
TS255 B5
TS0 B5
TS0 B4
TS1 B0
TS0 B1
TS0 B0
TS243 B5