TSI-8 AGERE [Agere Systems], TSI-8 Datasheet - Page 22

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TSI-8

Manufacturer Part Number
TSI-8
Description
8K x 8K Time-Slot Interchanger
Manufacturer
AGERE [Agere Systems]
Datasheet
TSI-8
8K x 8K Time-Slot Interchanger
Table 6-6. Microprocessor Port Timing—Read Cycle
22
22
Parameter
DATA[15:00]
ADDR[15:00]
t
t
t
t
t
t
t
t
t
t
t
t
t
t
23
24
25
26
27
28
29
30
31
32
33
34
35
36
PAR[1:0]
MPUCLK
R/W
DT
CS
AS
Address Setup
Address Hold
Chip Select Setup
Chip Select Hold
Address Strobe Setup
Address Strobe Hold
R/W Setup
R/W Hold
Data Output Enable
Data Clock to Valid
Data High-Impedance
DT High-Impedance to Valid
DT Clock to Out
DT Valid to High-Impedance
Figure 6-16. Microprocessor Port Timing—Read Cycle
t
t
t
t
t
34
23
27
29
25
t
t
24
28
Description
t
31
Hardware Design Guide, Revision 1
t
35
t
32
Min
5
1
5
1
5
1
5
1
1
1
1
1
t
t
t
26
30
35
November 2, 2005
Max
15
15
7
8
7
8
Agere Systems Inc.
t
33
t
36
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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