KS8893ML MICREL [Micrel Semiconductor], KS8893ML Datasheet
KS8893ML
Related parts for KS8893ML
KS8893ML Summary of contents
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... Both PHY units support 10BASE-T and 100BASE- TX. In addition, one PHY unit supports 100BASE- FX. The KS8893ML is the single power supply version with all the identical rich features of the KS8893M. 10/100 10/100 T/TX/FX ...
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Features • Proven Integrated 3-Port 10/100 Ethernet Switch – 3rd generation switch with three MACs and two PHYs fully compliant to IEEE 802.3u standard – Non-blocking switch fabric assures fast packet delivery by utilizing an 1K MAC address lookup table ...
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... Ordering Information Part Number Temperature Range o o KS8893M KS8893ML KS8893MI – + KSZ8993M Contacts Location Address Corporate HQ 2180 Fortune Drive Eastern USA 93 Branch Street Central USA 722 S. Denton Tap Suite 130 ...
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Revision History Revision Date 1.0 6/30/05 June 2005 Summary of Changes Initial release 4 M9999-063005 ...
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Contents General Description................................................................................................................................1 Functional Diagram ................................................................................................................................1 Features ...................................................................................................................................................2 Applications ............................................................................................................................................2 Ordering Information ..............................................................................................................................3 Contacts ..................................................................................................................................................3 Revision History......................................................................................................................................4 Contents ..................................................................................................................................................5 List of Figures .........................................................................................................................................9 List of Tables.........................................................................................................................................10 Pin Description and I/O Assignment...................................................................................................11 Pin Configuration..................................................................................................................................20 Functional Description .........................................................................................................................21 Functional Overview: Physical Layer ...
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IPv6 MLD Snooping.............................................................................................................................................................39 Port Mirroring Support........................................................................................................................................................40 IEEE 802.1Q VLAN Support ................................................................................................................................................40 QoS Priority Support...........................................................................................................................................................41 Port-Based Priority..............................................................................................................................................................41 802.1p-Based Priority..........................................................................................................................................................41 DiffServ-Based Priority .......................................................................................................................................................42 Rate Limiting Support .........................................................................................................................................................42 Unicast MAC Address Filtering..........................................................................................................................................42 Configuration Interface ....................................................................................................................................................... Master Serial Bus Configuration ..............................................................................................................................43 ...
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Register 33 (0x21): Port 2 Control 1 ..............................................................................................................................63 Register 49 (0x31): Port 3 Control 1 ..............................................................................................................................63 Register 18 (0x12): Port 1 Control 2 ..............................................................................................................................64 Register 34 (0x22): Port 2 Control 2 ..............................................................................................................................64 Register 50 (0x32): Port 3 Control 2 ..............................................................................................................................64 ...
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Register 111 (0x6F): TOS Priority Control Register 15..................................................................................................82 Register 112 (0x70): MAC Address Register 0 ..............................................................................................................82 Register 113 (0x71): MAC Address Register 1 ..............................................................................................................82 Register 114 (0x72): MAC Address Register 2 ..............................................................................................................82 Register 115 (0x73): MAC Address Register 3 ..............................................................................................................82 ...
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List of Figures Figure 1. Typical Straight Cable Connection ......................................................................................................................................24 Figure 2. Typical Crossover Cable Connection ..................................................................................................................................25 Figure 3. Auto-Negotiation and Parallel Operation ............................................................................................................................26 Figure 4. Destination Address Lookup Flow Chart, Stage 1 .............................................................................................................29 Figure 5. Destination Address Resolution Flow ...
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List of Tables Table 1. FX and TX Mode Selection .....................................................................................................................................................22 Table 2. MDI/MDI-X Pin Definitions.......................................................................................................................................................23 Table 3. MII Signals ................................................................................................................................................................................32 Table 4: RMII Signal Description ..........................................................................................................................................................33 Table 5: RMII Signal Connections ........................................................................................................................................................34 Table 6. SNI Signals...............................................................................................................................................................................34 Table 7. MII ...
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Pin Description and I/O Assignment Pin Number Pin Name 1 P1LED2 2 P1LED1 3 P1LED0 Note: 1. Ipu/O = Input with internal pull-up during reset, output pin otherwise. June 2005 (1) Type Description Ipu/O Port 1 LED Indicators (apply to ...
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Pin Number Pin Name 4 P2LED2 5 P2LED1 6 P2LED0 7 DGND 8 VDDIO Note Power supply. Gnd = Ground. Ipd = Input w/ internal pull-down. Ipu/O = Input with internal pull-up during reset, output pin otherwise. ...
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... For KS8893M, this is an input power pin for the 1.2V DDC digital core For KS8893ML, this is a 1.2V output power pin to OUT_1V2 supply the KS8893ML’s input power pins (pins 91 and 123), and V DDC Ipd LED display mode select See description in pins 1 and 4. ...
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Pin Number Pin Name 26 RMII_EN 27 HWPOVR 28 P2MDIXDIS 29 P2MDIX 30 P1ANEN 31 P1SPD 32 P1DPX 33 P1FFC PWRDN 37 AGND 38 VDDA 39 AGND 40 MUX1 41 MUX2 Note ...
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Pin Number Pin Name 42 AGND 43 VDDA 44 FXSD1 45 RXP1 46 RXM1 47 AGND 48 TXP1 49 TXM1 50 VDDATX 51 VDDARX 52 RXM2 53 RXP2 54 AGND 55 TXM2 56 TXP2 57 VDDA 58 AGND 59 TEST1 ...
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Pin Number Pin Name 70 LEDSEL0 71 SMTXEN 72 SMTXD3 73 SMTXD2 74 SMTXD1 75 SMTXD0 76 SMTXER 77 SMTXC / REFCLK 78 DGND 79 VDDIO 80 SMRXC 81 SMRXDV 82 SMRXD3 83 SMRXD2 84 SMRXD1 85 SMRXD0 86 SCOL ...
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Pin Number Pin Name 88 SCONF1 89 SCONF0 90 DGND 91 VDDC 92 UNUSED 93 UNUSED 94 MDC 95 MDIO 96 SPIQ 97 SCL 98 SDA 99 SPIS_N Note Power supply. Gnd = Ground Input. ...
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Pin Number Pin Name 100 PS1 101 PS0 102 UNUSED 103 UNUSED Note Input. June 2005 (1) Type Description I Serial bus configuration pins to select mode of access to KS8893M internal registers. I [PS1, PS0] = ...
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Pin Number Pin Name 104 UNUSED 105 UNUSED 106 DGND 107 VDDIO 108 UNUSED 109 UNUSED 110 UNUSED 111 UNUSED 112 UNUSED 113 UNUSED 114 UNUSED 115 UNUSED 116 UNUSED 117 UNUSED 118 UNUSED 119 UNUSED 120 UNUSED 121 UNUSED ...
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Pin Configuration 103 UNUSED 104 UNUSED 105 UNUSED 106 DGND 107 VDDIO 108 UNUSED 109 UNUSED 110 UNUSED 111 UNUSED 112 UNUSED 113 UNUSED 114 UNUSED 115 UNUSED 116 UNUSED 117 UNUSED 118 UNUSED 119 UNUSED 120 UNUSED 121 UNUSED ...
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... On the media side, the KS8893M supports IEEE 802.3 10BASE-T and 100BASE-TX on both PHY ports, and also 100BASE-FX on PHY port 1, which allows the KS8893M to be used as a media converter. The KS8893ML is the single supply version with all the identical rich features of the KS8893M. In the KS8893ML version, pin number 22 provides 1.2V output power to the KS8893ML’ the Pin Description table for information about pin 22 (Pin Description and I/0 Assignment) ...
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PLL Clock Synthesizer The KS8893M generates 125MHz, 31.25MHz, 25MHz, and 10MHz clocks for system timing. Internal clocks are generated from an external 25MHz crystal or oscillator. In RMII mode, these internal clocks are generated from an external 50MHz oscillator or ...
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Transmit The 10BASE-T driver is incorporated with the 100BASE-TX driver to allow for transmission using the same magnetics. They are internally wave-shaped and pre-emphasized into outputs with a typical 2.3V amplitude. The harmonic contents are at least 27dB below ...
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Straight Cable A straight cable connects an MDI device to an MDI-X device MDI-X device to an MDI device. The following diagram depicts a typical straight cable connection between a NIC card (MDI) and a switch, or hub ...
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Crossover Cable A crossover cable connects an MDI device to another MDI device MDI-X device to another MDI-X device. The following diagram shows a typical crossover cable connection between two switches or hubs (two MDI-X devices). 10/100 Ethernet ...
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Start Auto Negotiation Force Link Setting Yes Bypass Auto Negotiation and Set Link Mode Figure 3. Auto-Negotiation and Parallel Operation June 2005 N Parallel Operation o Attempt Auto Listen for 100BASE-TX Negotiation Idles Join Flow Link Mode Set ? Yes ...
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LinkMD Cable Diagnostics The LinkMD feature utilizes time domain reflectometry (TDR) to analyze the cabling plant for common cabling problems such as open circuits, short circuits and impedance mismatches. LinkMD works by sending a pulse of known amplitude and duration ...
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Functional Overview: MAC and Switch Address Lookup The internal lookup table stores MAC addresses and their associated information. It contains a 1K unicast address table plus switching information. The KS8893M is guaranteed to learn 1K addresses and distinguishes itself from ...
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PTF1= NULL Search complete. Get PTF1 from Static MAC Table Search complete. Get PTF1 from Dynamic MAC Table Figure 4. Destination Address Lookup Flow Chart, Stage 1 June 2005 Start - Search VLAN table NO VLAN ID - Ingress VLAN ...
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Spanning Tree Process IGMP Process Port Mirror Process Port VLAN Membership Check Figure 5. Destination Address Resolution Flow Chart, Stage 2 The KS8893M will not forward the following packets: 1. Error packets These include framing errors, Frame Check Sequence (FCS) ...
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Switching Engine The KS8893M features a high-performance switching engine to move data to and from the MACs’ packet buffers. It operates in store and forward mode, while the efficient switching mechanism reduces overall latency. The switching engine has a 32kB ...
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If a collision occurs, the binary exponential back-off algorithm is skipped and carrier sense is generated immediately, thus reducing the chance of further collisions and carrier sense is maintained to prevent packet reception. ...
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The MII operates in either PHY mode or MAC mode. The data interface is a nibble wide and runs at ¼ the network bit rate (not encoded). Additional signals on the transmit side indicate when data is valid or when ...
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The KS8893M filters error frames, and thus does not implement the RX_ER output signal. To detect error frames from RMII PHY devices, the SMTXER input signal of the KS8893M is connected to the RXER output signal of the RMII PHY ...
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The SNI interface is a bit wide data interface and therefore runs at the network bit rate (not encoded). An additional signal on the transmit side indicates when data is valid. Similarly, the receive side has an indicator that conveys ...
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Serial Management Interface (SMI) The SMI is the KS8893M non-standard MIIM interface that provides access to all KS8893M configuration registers. This interface allows an external device to completely monitor and control the states of the KS8893M. The SMI interface consists ...
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Advanced Switch Functions Spanning Tree Support To support spanning tree, port 3 is the designated port for the processor. The other ports (port 1 and port 2) can be configured in one of the five spanning tree states via “transmit ...
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Special Tagging Mode Special Tagging Mode is designed for spanning tree protocol IGMP snooping and is flexible for use in other applications. Special Tagging, similar to 802.1Q Tagging, requires software to change network drivers to insert/modify/strip/interpret the special tag. This ...
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For packets from regular ports (port 1 & port 2) to port 3, the port mask is used to tell the processor which port the packets were received on, defined as follows: “0001”, packet from port 1 “0010”, packet from ...
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Port Mirroring Support KS8893M supports “Port Mirroring” comprehensively as: “receive only” mirror on a port All the packets received on the port are mirrored on the sniffer port. For example, port 1 is programmed to be “receive sniff” and port ...
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FID+SA found in Dynamic MAC Table? No Yes Advanced VLAN features, such as “Ingress VLAN filtering” and “Discard Non PVID packets” are also supported by the KS8893M. These features can be set on a per port basis, and are defined ...
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The KS8893M provides the option to insert or remove the priority tagged frame's header at each individual egress port. This ...
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This function is useful in preventing the broadcast of unicast packets that could degrade the quality of the port in applications such as voice over Internet Protocol (VoIP). Configuration Interface The KS8893M can operate as both a managed switch and ...
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I C Slave Serial Bus Configuration In managed mode, the KS8893M can be configured (external controller/CPU) has complete programming access to the KS8893M’s 142 registers. Programming access includes the Global Registers, Port Registers, Advanced Control Registers ...
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The following is a sample procedure for programming the KS8893M using the SPI bus the board level, connect the KS8893M pins as follows: KS8893M Pin # Enable SPI slave mode by setting the ...
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SPIS_N SPIC SPID SPIQ READ COMMAND SPIS_N SPIC SPID SPIQ WRITE COMMAND SPIS_N SPIC SPID SPIQ Byte 2 SPIS_N SPIC SPID SPIQ READ COMMAND SPIS_N ...
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Loopback Support The KS8893M provides loopback support for remote diagnostic of failure. In loopback mode, the speed at both PHY ports needs to be set to 100BASE-TX. Two types of loopback are supported: Far-end Loopback and Near- end (Remote) Loopback. ...
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Near-end (Remote) Loopback Near-end (Remote) loopback is conducted at either PHY port 1 or PHY port 2.of the KS8893M. The loopback path starts at the PHY port’s receive inputs (RXPx/RXMx), wraps around at the same PHY port’s PMD/PMA, and ends ...
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MII Management (MIIM) Registers The MIIM interface is used to access the MII PHY registers, defined in this section. The SPI, I interfaces can also be used to access some of these registers. The latter three interfaces use a different ...
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PHY1 Register 0 (PHYAD = 0x1, REGAD = 0x0): MII Basic Control PHY2 Register 0 (PHYAD = 0x2, REGAD = 0x0): MII Basic Control Bit Name R/W 15 Soft reset RO 14 Loopback R/W 13 Force 100 R ...
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PHY1 Register 1 (PHYAD = 0x1, REGAD = 0x1): MII Basic Status PHY2 Register 1 (PHYAD = 0x2, REGAD = 0x1): MII Basic Status Bit Name R capable RO 14 100 Full RO capable 13 100 Half RO ...
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PHY1 Register 4 (PHYAD = 0x1, REGAD = 0x4): Auto-Negotiation Advertisement Ability PHY2 Register 4 (PHYAD = 0x2, REGAD = 0x4): Auto-Negotiation Advertisement Ability Bit Name R/W 15 Next page RO 14 Reserved RO 13 Remote fault RO 12-11 Reserved ...
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PHY1 Register 29 (PHYAD = 0x1, REGAD = 0x1D): LinkMD Control/Status PHY2 Register 29 (PHYAD = 0x2, REGAD = 0x1D): LinkMD Control/Status Bit Name R/W 15 Vct_enable R/W (SC) 14-13 Vct_result RO 12 Vct 10M Short RO 11-9 Reserved RO ...
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Register Map: Switch & PHY (8-bit registers) Global Registers Register (Decimal) Register (Hex) 0-1 0x00-0x01 2-15 0x02-0x0F Port Registers Register (Decimal) Register (Hex) 16-29 0x10-0x1D 30-31 0x1E-0x1F 32-45 0x20-0x2D 46-47 0x2E-0x2F 48-57 0x30-0x39 58-62 0x3A-0x3E 63 0x3F 64-95 0x40-0x5F Advanced ...
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Register 1 (0x01): Chip ID1 / Start Switch Bit Name R/W 7-4 Chip ID RO 3-1 Revision Start Switch RW Register 2 (0x02): Global Control 0 Bit Name R/W 7 New Back-off R/W Enable 6-4 Reserved R/W ...
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Register 3 (0x03): Global Control 1 Bit Name R/W 7 Pass All R/W Frames 6 Reserved R/W 5 IEEE 802.3x R/W Transmit Direction Flow Control Enable 4 IEEE 802.3x R/W Receive Direction Flow Control Enable 3 Frame Length R/W Field ...
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Register 4 (0x04): Global Control 2 (continued) Bit Name R/W 4 Flow Control R/W and Back Pressure Fair Mode 3 No Excessive R/W Collision Drop 2 Huge Packet R/W Support 1 Legal R/W Maximum Packet Size Check Enable Priority Buffer ...
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Register 5 (0x05): Global Control 3 (continued) Bit Name R/W 3 Weighted R/W Fair Queue Enable 2-1 Reserved R/W 0 Sniff Mode R/W Select Register 6 (0x06): Global Control 4 Bit Name R/W 7 Repeater R/W Mode 6 Switch MII ...
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Register 6 (0x06): Global Control 4 (continued) Bit Name R/W 4 Switch MII R/W 10BT 3 Null VID R/W Replacement 2-0 Broadcast R/W Storm Protection (1) Rate Bit [10:8] Register 7 (0x07): Global Control 5 Bit Name R/W 7-0 Broadcast ...
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Register 11 (0x0B): Global Control 9 Bit Name R/W Description 7 LEDSEL1 R/W LED mode select See description in bit 1 of this register. 6-5 Reserved R/W Reserved Do not change the default values. 4 Reserved R/W Testing mode. Set ...
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Register 13 (0x0D): Global Control 11 Bit Name R/W Description 7-6 Tag_0x7 R/W IEEE 802.1p mapping. The value in this field is used as the frame’s priority when its IEEE 802.1p tag has a value of 0x7. 5-4 Tag_0x6 R/W ...
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Port Registers The following registers are used to enable features that are assigned on a per port basis. The register bit assignments are the same for all ports, but the address for each port is different, as indicated. Register 16 ...
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Register 17 (0x11): Port 1 Control 1 Register 33 (0x21): Port 2 Control 1 Register 49 (0x31): Port 3 Control 1 Bit Name R/W 7 Sniffer Port R/W 6 Receive Sniff R/W 5 Transmit Sniff R/W 4 Double Tag R/W ...
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Register 18 (0x12): Port 1 Control 2 Register 34 (0x22): Port 2 Control 2 Register 50 (0x32): Port 3 Control 2 Bit Name R/W 7 Reserved R/W 6 Ingress VLAN R/W Filtering 5 Discard non R/W PVID Packets 4 Force ...
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Register 19 (0x13): Port 1 Control 3 Register 35 (0x23): Port 2 Control 3 Register 51 (0x33): Port 3 Control 3 Bit Name R/W 7-0 Default Tag R/W [15:8] Register 20 (0x14): Port 1 Control 4 Register 36 (0x24): Port ...
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Register 22 (0x16): Port 1 Control 6 Register 38 (0x26): Port 2 Control 6 Register 54 (0x36): Port 3 Control 6 Bit Name R/W 7-4 Ingress Pri1 R/W Rate 3-0 Ingress Pri0 R/W Rate June 2005 Description Ingress data rate ...
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Register 23 (0x17): Port 1 Control 7 Register 39 (0x27): Port 2 Control 7 Register 55 (0x37): Port 3 Control 7 Bit Name R/W 7-4 Ingress Pri3 R/W Rate 3-0 Ingress Pri2 R/W Rate June 2005 Description Ingress data rate ...
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Register 24 (0x18): Port 1 Control 8 Register 40 (0x28): Port 2 Control 8 Register 56 (0x38): Port 3 Control 8 Bit Name R/W 7-4 Egress Pri1 R/W Rate 3-0 Egress Pri0 R/W Rate June 2005 Description Egress data rate ...
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Register 25 (0x19): Port 1 Control 9 Register 41 (0x29): Port 2 Control 9 Register 57 (0x39): Port 3 Control 9 Bit Name R/W 7-4 Egress Pri3 R/W Rate 3-0 Egress Pri2 R/W Rate June 2005 Description Egress data rate ...
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Note: Most of the contents in registers 26-31 and registers 42-47 for ports 1 and 2, respectively, can also be accessed with the MIIM PHY registers. Register 26 (0x1A): Port 1 PHY Special Control/Status Register 42 (0x2A): Port 2 PHY ...
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Register 28 (0x1C): Port 1 Control 12 Register 44 (0x2C): Port 2 Control 12 Register 60 (0x3C): Reserved, not applied to port 3 Bit Name R/W 7 Auto R/W Negotiation Enable 6 Force Speed R/W 5 Force Duplex R/W 4 ...
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Register 29 (0x1D): Port 1 Control 13 Register 45 (0x2D): Port 2 Control 13 Register 61 (0x3D): Reserved, not applied to port 3 Bit Name R/W 7 LED Off R/W 6 Txdis R/W 5 Restart AN R/W 4 Disable Far- ...
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Register 30 (0x1E): Port 1 Status 0 Register 46 (0x2E): Port 2 Status 0 Register 62 (0x3E): Reserved, not applied to port 3 Bit Name R/W MDI-X Status Done 6 RO Link Good 5 RO Partner Flow ...
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Register 31 (0x1F): Port 1 Status 1 (continued) Register 47 (0x2F): Port 2 Status 1 (continued) Register 63 (0x3F): Port 3 Status 1 (continued) Bit Name R/W 2 Operation RO Speed 1 Operation RO Duplex 0 Far-end Fault RO Advanced ...
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Register 97 (0x61): TOS Priority Control Register 1 Bit Name R/W 7-6 DSCP[15:14] R/W 5-4 DSCP[13:12] R/W 3-2 DSCP[11:10] R/W 1-0 DSCP[9:8] R/W Register 98 (0x62): TOS Priority Control Register 2 Bit Name R/W 7-6 DSCP[23:22] R/W 5-4 DSCP[21:20] R/W ...
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Register 99 (0x63): TOS Priority Control Register 3 Bit Name R/W 7-6 DSCP[31:30] R/W 5-4 DSCP[29:28] R/W 3-2 DSCP[27:26] R/W 1-0 DSCP[25:24] R/W Register 100 (0x64): TOS Priority Control Register 4 Bit Name R/W 7-6 DSCP[39:38] R/W 5-4 DSCP[37:36] R/W ...
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Register 101 (0x65): TOS Priority Control Register 5 Bit Name R/W 7-6 DSCP[47:46] R/W 5-4 DSCP[45:44] R/W 3-2 DSCP[43:42] R/W 1-0 DSCP[41:40] R/W Register 102 (0x66): TOS Priority Control Register 6 Bit Name R/W 7-6 DSCP[55:54] R/W 5-4 DSCP[53:52] R/W ...
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Register 103 (0x67): TOS Priority Control Register 7 Bit Name R/W 7-6 DSCP[63:62] R/W 5-4 DSCP[61:60] R/W 3-2 DSCP[59:58] R/W 1-0 DSCP[57:56] R/W Register 104 (0x68): TOS Priority Control Register 8 Bit Name R/W 7-6 DSCP[71:70] R/W 5-4 DSCP[69:68] R/W ...
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Register 105 (0x69): TOS Priority Control Register 9 Bit Name R/W 7-6 DSCP[79:78] R/W 5-4 DSCP[77:76] R/W 3-2 DSCP[75:74] R/W 1-0 DSCP[73:72] R/W Register 106 (0x6A): TOS Priority Control Register 10 Bit Name R/W 7-6 DSCP[87:86] R/W 5-4 DSCP[85:84] R/W ...
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Register 107 (0x6B): TOS Priority Control Register 11 Bit Name R/W 7-6 DSCP[95:94] R/W 5-4 DSCP[93:92] R/W 3-2 DSCP[91:90] R/W 1-0 DSCP[89:88] R/W Register 108 (0x6C): TOS Priority Control Register 12 Bit Name R/W 7-6 DSCP[103:102] R/W 5-4 DSCP[101:100] R/W ...
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Register 109 (0x6D): TOS Priority Control Register 13 Bit Name R/W 7-6 DSCP[111:110] R/W 5-4 DSCP[109:108] R/W 3-2 DSCP[107:106] R/W 1-0 DSCP[105:104] R/W Register 110 (0x6E): TOS Priority Control Register 14 Bit Name R/W 7-6 DSCP[119:118] R/W 5-4 DSCP[117:116] R/W ...
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Register 111 (0x6F): TOS Priority Control Register 15 Bit Name R/W 7-6 DSCP[127:126] R/W 5-4 DSCP[125:124] R/W 3-2 DSCP[123:122] R/W 1-0 DSCP[121:120] R/W Registers 112 to 117 Registers 112 to 117 contain the switch engine’s MAC address. This 48-bit address ...
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Registers 118 to 120 Registers 118 to 120 are User Defined Registers (UDRs). These are general purpose read/write registers that can be used to pass user defined control and status information between the KS8893M and the external processor. Register 118 ...
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Register 124 (0x7C): Indirect Data Register 7 Bit Name R/W 7-0 Indirect Data R/W [63:56] Register 125 (0x7D): Indirect Data Register 6 Bit Name R/W 7-0 Indirect Data R/W [55:48] Register 126 (0x7E): Indirect Data Register 5 Bit Name R/W ...
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Register 133 (0x85): Digital Testing Control 0 Bit Name R/W 7-0 Reserved R/W Register 134 (0x86): Analog Testing Control 0 Bit Name R/W 7-0 Reserved R/W Register 135 (0x87): Analog Testing Control 1 Bit Name R/W 7-0 Reserved R/W Register ...
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Static MAC Address Table The KS8893M supports both a static and a dynamic MAC address table. In response to a Destination Address (DA) look up, the KS8893M searches both tables to make a packet forwarding decision. In response to a ...
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Static Address Table Write (Write the 8 Write to reg. 124 (0x7C), static table bits [57:56] Write to reg. 125 (0x7D), static table bits [55:48] Write to reg. 126 (0x7E), static table bits [47:40] Write to reg. 127 (0x7F), ...
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VLAN Table Write (write the 7 Write to reg. 129 (0x81), VLAN table bits [19:16] Write to reg. 130 (0x82), VLAN table bits [15:8] Write to reg. 131 (0x83), VLAN table bits [7:0] Write to reg. 121 (0x79) with ...
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MIB (Management Information Base) Counters The KS8893M provides 34 MIB counters per port. These counters are used to monitor the port activity for network management. The MIB counters have two format groups: “Per Port” and “All Port Dropped Packet.” Bit ...
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Rx256to511Octets 0x12 Rx512to1023Octets 0x13 Rx1024to1522Octets 0x14 TxLoPriorityByte 0x15 TxHiPriorityByte 0x16 TxLateCollision 0x17 TxPausePkts 0x18 TxBroadcastPkts 0x19 TxMulticastPkts 0x1A TxUnicastPkts 0x1B TxDeferred 0x1C TxTotalCollision 0x1D TxExcessiveCollision 0x1E TxSingleCollision 0x1F TxMultipleCollision Table 20. Port 1’s “Per Port” MIB Counters Indirect Memory ...
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Examples: 1. MIB Counter Read (Read port 1 “Rx64Octets” Counter) Write to reg. 121 (0x79) with 0x1c Write to reg. 122 (0x7A) with 0x0e Then Read reg. 128 (0x80), overflow bit [31] Read reg. 129 (0x81), counter bits [23:16] Read ...
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Absolute Maximum Ratings Description Supply Storage Supply Voltage Input Voltage (all inputs) Output Voltage (all outputs) Lead Temperature (soldering, 10 sec) Storage Temperature ( Note: 1. Exceeding the absolute maximum rating may damage the device. Stresses greater than ...
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... Electrical Characteristics Parameter Supply Current - Single-supply KS8893ML device only 100BASE-TX (transceiver + digital I/O) 10BASE-T (transceiver + digital I/O) Supply Current - Dual-supply KS8893M device only 100BASE-TX (analog core + PLL + digital core) 100BASE-TX (transceiver + digital I/O) 10BASE-T (analog core + PLL + digital core) 10BASE-T (transceiver + digital I/O) TTL Inputs ...
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Electrical Characteristics (continued) Parameter 10BASE-T Receive Squelch Threshold 10BASE-T Transmit (measured differentially after 1:1 transformer) VDDATX = 3.3V Peak Differential Output Voltage Output Jitter Note 25°C. Specification for packaged product only. June 2005 (1) Symbol Condition 5 ...
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Timing Specifications EEPROM Timing Receive Timing SCL SDA Figure 14. EEPROM Interface Input Timing Diagram Transmit Timing SCL SDA Figure 15. EEPROM Interface Output Timing Diagram Timing Parameter Description Clock cycle t cyc1 Setup time t s1 Hold time t ...
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SNI Timing Receive Timing MTXC MTXEN MTXD[0] Transmit Timing MRXC MRXDV MCOL MRXD[0] Timing Parameter Description Clock cycle t cyc2 Setup time t s2 Hold time t h2 Output valid t ov2 June 2005 ts2 tcyc2 th2 Figure 16. SNI ...
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MII Timing MAC Mode MII Timing Figure ...
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PHY Mode MII Timing Transmit Timing MTXCLK MTXEN MTXER MTXD[3:0] Figure 20. PHY Mode MII Timing – Data Received from MII Receive Timing MRXCLK MRXDV MRXD[3:0] Timing Parameter Description tcyc4 Clock cycle (100BASE-TX) 100BASE-TX tcyc4 Clock cycle 10BASE-T (10BASE-T) ts4 ...
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RMII Timing Receive Tim ing ...
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SPI Timing Input Timing SPIS_N tCHSL SPIC tDVCH SPID SPIQ Timing Parameter fC tCHSL tSLCH tCHSH tSHCH tSHSL tDVCH tCHDX tCLCH tCHCL tDLDH tDHDL June 2005 tSLCH tCHSH tCHDX tCLCH MSB tDLDH tDHDL High Impedance Figure 24. SPI Input Timing ...
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Output Timing SPIS_N SPIC SPIQ SPID Timing Parameter fC tCLQX tCLQV tCH tCL tQLQH tQHQL tSHQZ June 2005 tCH tCLQV tCLQX Figure 25. SPI Output Timing Description Clock frequency SPIQ hold time Clock low to SPIQ valid Clock high time ...
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Auto-Negotiation Timing A uto-N egotiation - F ast ulse T im ing Timing Parameter Description t FLP burst to FLP burst BTB t FLP ...
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... The KS8893M should be powered up with the VDD core voltages (VDDC, VDDA, VDDAP) applied before the VDDIO and transceiver voltages (VDDIO, VDDATX, VDDARX). In the worst case, VDD core, VDDIO and transceiver voltages can be applied simultaneously. For the KS8893ML, there is no power sequence requirement. Additional, reset timing requirements are summarized in the following figure and table. ...
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Reset Circuit The reset circuit in Figure 28 is recommended for powering up the KS8893M if reset is triggered only by the power supply. KS8893M The reset circuit in Figure 29 is recommended for applications where reset is driven by ...
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Selection of Isolation Transformers An 1:1 isolation transformer is required at the line interface. An isolation transformer with integrated common- mode choke is recommended for exceeding FCC requirements. The following table gives recommended transformer characteristics. Parameter Turns ratio Open-circuit inductance ...
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Package Information MICREL, INC. 1849 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL: +1 (408) 944-0800 The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for ...