KS8893ML MICREL [Micrel Semiconductor], KS8893ML Datasheet - Page 43

• Manufacturer Part Number: KS8893ML
• Description: Integrated 3-Port 10/100 Managed Switch with PHYs Preliminary Data Sheet Rev. 1.0
• Manufacturer: MICREL [Micrel Semiconductor]

This function is useful in preventing the broadcast of unicast packets that could degrade the quality of the port in
applications such as voice over Internet Protocol (VoIP).
Configuration Interface
The KS8893M can operate as both a managed switch and an unmanaged switch.
In unmanaged mode, the KS8893M is typically programmed using an EEPROM. If no EEPROM is present, the
KS8893M is configured using its default register settings. Some defaults settings are configured via strap-in pin
options. The strap-in pins are indicated in the “KS8893M Pin Description and I/O Assignment” table.
I
With an additional I
“broadcast storm protection” and “rate control” without the need of an external processor.
For KS8893M I
(as defined in the KS8893M register map) with the exception of the “Read Only” status registers. After the de-
assertion of reset, the KS8893M sequentially reads in the configuration data for all 121 registers, starting from
register 0. The configuration access time (t
The following is a sample procedure for programming the KS8893M with a pre-configured EEPROM:
1. Connect the KS8893M to the EEPROM by joining the SCL and SDA signals of the respective devices. For the
2. Enable I
3. Check to ensure that the KS8893M reset signal input, RST_N (pin 67), is properly connected to the external
4. Program the desired configuration data into the EEPROM.
5. Place the EEPROM on the board and power up the board.
6. Assert an active-low reset to the RST_N pin of the KS8893M. After reset is de-asserted, the KS8893M begins
Note: For proper operation, check to ensure that the KS8893M PWRDN input signal (pin 36) is not asserted
during the reset operation. The PWRDN input is active low.
2
June 2005
C Master Serial Bus Configuration
KS8893M, SCL is pin 97 and SDA is pin 98.
“00”.
reset source at the board level.
reading the configuration data from the EEPROM. The KS8893M checks that the first byte read from the
EEPROM is “88”. If this value is correct, EEPROM configuration continues. If not, EEPROM configuration
access is denied and all other data sent from the EEPROM is ignored by the KS8893M. The configuration
access time (t
RST_N
SCL
SDA
2
C master mode by setting the KS8893M strap-in pins, PS[1:0] (pins 100 and 101, respectively) to
2
C Master configuration, the EEPROM stores the configuration data for register 0 to register 120
prgm
2
) is less than 15ms.
C (“2-wire”) EEPROM, the KS8893M can perform more advanced switch features like
Figure 7. KS8893M EEPROM Configuration Timing Diagram
prgm
) is less than 15 ms, as depicted in the following figure.
43
t
prgm
....
....
....
<15 ms
M9999-063005