KS8893ML MICREL [Micrel Semiconductor], KS8893ML Datasheet - Page 9

• Manufacturer Part Number: KS8893ML
• Description: Integrated 3-Port 10/100 Managed Switch with PHYs Preliminary Data Sheet Rev. 1.0
• Manufacturer: MICREL [Micrel Semiconductor]

Micrel
KS8893M/ML/MI
List of Figures
Figure 1. Typical Straight Cable Connection ......................................................................................................................................24
Figure 2. Typical Crossover Cable Connection ..................................................................................................................................25
Figure 3. Auto-Negotiation and Parallel Operation ............................................................................................................................26
Figure 4. Destination Address Lookup Flow Chart, Stage 1 .............................................................................................................29
Figure 5. Destination Address Resolution Flow Chart, Stage 2 .......................................................................................................30
Figure 6. 802.1p Priority Field Format .................................................................................................................................................41
Figure 7. KS8893M EEPROM Configuration Timing Diagram ...........................................................................................................43
Figure 8. SPI Write Data Cycle..............................................................................................................................................................45
Figure 9. SPI Read Data Cycle ..............................................................................................................................................................46
Figure 10. SPI Multiple Write.................................................................................................................................................................46
Figure 11. SPI Multiple Read.................................................................................................................................................................46
Figure 12: Far-End Loopback Path ......................................................................................................................................................47
Figure 13. Near-end (Remote) Loopback Path....................................................................................................................................48
Figure 14. EEPROM Interface Input Timing Diagram .........................................................................................................................95
Figure 15. EEPROM Interface Output Timing Diagram ......................................................................................................................95
Figure 16. SNI Input Timing Diagram...................................................................................................................................................96
Figure 17. SNI Output Timing Diagram................................................................................................................................................96
Figure 18. MAC Mode MII Timing – Data Received from MII..............................................................................................................97
Figure 19. MAC Mode MII Timing – Data Input to MII .........................................................................................................................97
Figure 20. PHY Mode MII Timing – Data Received from MII ..............................................................................................................98
Figure 21. PHY Mode MII Timing – Data Input to MII ..........................................................................................................................98
Figure 22: RMII Timing – Data Received from RMII............................................................................................................................99
Figure 23: RMII Timing – Data Input to RMII........................................................................................................................................99
Figure 24. SPI Input Timing.................................................................................................................................................................100
Figure 25. SPI Output Timing..............................................................................................................................................................101
Figure 26: Auto-Negotiation Timing...................................................................................................................................................102
Figure 27. Reset Timing ......................................................................................................................................................................103
Figure 28. Recommended Reset Circuit............................................................................................................................................104
Figure 29. Recommended Reset Circuit for interfacing with CPU/FPGA Reset Output...............................................................104
Figure 30. 128-Pin PQFP Package......................................................................................................................................................106
June 2005
9
M9999-063005