AT91RM3400-AI-001 ATMEL [ATMEL Corporation], AT91RM3400-AI-001 Datasheet - Page 149

• Manufacturer Part Number: AT91RM3400-AI-001
• Manufacturer: ATMEL [ATMEL Corporation]

PMC Clock Generator PLL B Register
Register Name: CKGR_PLLBR
Access Type:
• DIVB: Divider B
• PLLBCOUNT: PLL B Counter
Specifies the number of slow clock cycles before the LOCKB bit is set in PMC_SR after CKGR_PLLBR is written.
• OUTB: PLLB Clock Frequency Range
• MULB: PLL B Multiplier
0 = The PLL B is deactivated.
1 up to 2047 = The PLLB Clock frequency is the PLL B input frequency multiplied by MULB + 1.
• USB_96M: Divider by 2 Enable (only on ARM9-based Systems)
0 = USB ports clocks are PLLB Clock, therefore the PMC Clock Generator must be programmed for the PLLB Clock to be
48 MHz.
1 = USB ports clocks are PLLB Clock divided by 2, therefore the PMC Clock Generator must be programmed for the PLLB
Clock to be 96 MHz.
1790A–ATARM–11/03
DIVB
0
1
2 - 255
31
23
15
–
7
0
0
1
1
OUTB
OUTB
Read/Write
30
22
14
–
6
0
1
0
1
29
21
13
–
5
Divider Selected
Divider output is 0
Divider is bypassed
Divider output is the selected clock divided by DIVB.
PLLB Clock Frequency Range
80 MHz to 160 MHz
Reserved
150 MHz to 240 MHz
Reserved
USB_96M
28
20
12
4
MULB
DIVB
27
19
11
–
3
PLLBCOUNT
26
18
10
2
MULB
AT91RM3400
25
17
9
1
24
16
8
0
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