AT91RM3400-AI-001 ATMEL [ATMEL Corporation], AT91RM3400-AI-001 Datasheet - Page 256

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AT91RM3400-AI-001

Manufacturer Part Number
AT91RM3400-AI-001
Description
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
Figure 88. TWI Write in Master Mode
256
AT91RM3400
TWI_THR = data to send
Yes
TWI_CR = TWI_SVDIS + TWI_MSEN
Set the Master Mode register:
Internal address size = 0?
Write ==> bit MREAD = 0
TWI_THR = Data to send
TWI_CR = TWI_START
Set the control register:
- Device slave address
TWI_CR = TWI_STOP
- Internal address size
- Transfer direction bit
Load transmit register
TWI_CWGR = clock
Read status register
Read status register
Start the transfer
Stop the transfer
- Master enable
- Slave disable
Set TWI clock:
TXCOMP = 0?
Data to send?
TXRDY = 0?
Yes
START
END
Yes
Set theinternal address
TWI_IADR = address
1790A–ATARM–11/03

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