AT91RM3400-AI-001 ATMEL [ATMEL Corporation], AT91RM3400-AI-001 Datasheet - Page 79
AT91RM3400-AI-001
Manufacturer Part Number
AT91RM3400-AI-001
Description
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT91RM3400-AI-001.pdf
(461 pages)
- Current page: 79 of 461
- Download datasheet (6Mb)
Memory Controller (MC)
Overview
1790A–ATARM–11/03
The Memory Controller (MC) manages the ASB bus and controls accesses requested
by the masters, typically the ARM7TDMI processor and the Peripheral Data Controller.
It features a simple bus arbiter, an address decoder, an abort status and a misalignment
detector. In addition, the MC contains a Memory Protection Unit (MPU) consisting of 16
areas that can be protected against write and/or user accesses. Access to peripherals
can be protected in the same way.
Main features of the AT91RM3400 Memory Controller are:
•
•
•
•
•
•
Bus Arbiter
–
Address Decoder Provides Selection Signals for
–
–
Abort Status Registers
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–
Misalignment Detector
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Remap Command
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16-area Memory Protection Unit
–
–
–
Handles Requests from the ARM7TDMI and the Peripheral Data Controller
Up to Four Internal 1-Mbyte Memory Areas
One 256-Mbyte Embedded Peripheral Area
Source, Type and All Parameters of the Access Leading to an Abort are
Saved
Facilitates Debug by Detection of Bad Pointers
Alignment Checking of All Data Accesses
Abort Generation in Case of Misalignment
Allows Remapping of an Internal SRAM in Place of the Internal ROM
Allows Handling of Dynamic Interrupt Vectors
Individually Programmable Size Between 1K Bytes and 64M Bytes
Individually Programmable Protection Against Write and/or User Access
Peripheral Protection Against Write and/or User Access
AT91RM3400
79
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