AT91RM3400-AI-001 ATMEL [ATMEL Corporation], AT91RM3400-AI-001 Datasheet - Page 27
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AT91RM3400-AI-001
Manufacturer Part Number
AT91RM3400-AI-001
Description
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT91RM3400-AI-001.pdf
(461 pages)
- Current page: 27 of 461
- Download datasheet (6Mb)
Modes and Exception
Handling
1790A–ATARM–11/03
.
Table 7. ARM7TDMI ARM Modes and Registers Layout
Registers R0 to R7 are unbanked registers. This means that each of them refers to the same
32-bit physical register in all processor modes. They are general-purpose registers, with no
special uses managed by the architecture, and can be used wherever an instruction allows a
general-purpose register to be specified.
Registers R8 to R14 are banked registers. This means that each of them depends on the cur-
rent mode of the processor.
All exceptions have banked registers for R14 and R13.
After an exception, R14 holds the return address for exception processing. This address is
used to return after the exception is processed, as well as to address the instruction that
caused the exception.
R13 is banked across exception modes to provide each exception handler with a private stack
pointer.
The fast interrupt mode also banks registers 8 to 12 so that interrupt processing can begin
without having to save these registers.
User and
System
Mode
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
PC
CPSR
Supervisor
Mode
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13_SVC
R14_SVC
PC
CPSR
SPSR_SVC
Abort Mode
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13_ABORT
R14_ABORT
PC
CPSR
SPSR_ABORT
Undefined
Mode
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13_UNDEF
R14_UNDEF
PC
CPSR
SPSR_UNDEF
Interrupt
Mode
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13_IRQ
R14_IRQ
PC
CPSR
SPSR_IRQ
Mode-specific banked registers
AT91RM3400
Fast
Interrupt
Mode
R0
R1
R2
R3
R4
R5
R6
R7
R8_FIQ
R9_FIQ
R10_FIQ
R11_FIQ
R12_FIQ
R13_FIQ
R14_FIQ
PC
CPSR
SPSR_FIQ
27
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