AT91RM3400-AI-001 ATMEL [ATMEL Corporation], AT91RM3400-AI-001 Datasheet - Page 232
AT91RM3400-AI-001
Manufacturer Part Number
AT91RM3400-AI-001
Description
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT91RM3400-AI-001.pdf
(461 pages)
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Product Dependencies
I/O Lines
Power
Management
Interrupt
Functional Description
Master Mode
Operations
Fixed Peripheral
Select
Variable Peripheral
Select
232
AT91RM3400
The pins used for interfacing the compliant external devices may be multiplexed with PIO
lines. The programmer must first program the PIO controllers to assign the SPI pins to their
peripheral functions.
The SPI may be clocked through the Power Management Controller (PMC), thus the program-
mer must first have to configure the PMC to enable the SPI clock.
The SPI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC).
Handling the SPI interrupt requires programming the AIC before configuring the SPI.
When configured in Master Mode, the Serial Peripheral Interface controls data transfers to and
from the slave(s) connected to the SPI bus. The SPI drives the chip select(s) to the slave(s)
and the serial clock (SPCK). After enabling the SPI, a data transfer begins when the core
writes to the SPI_TDR (Transmit Data Register).
Transmit and Receive buffers maintain the data flow at a constant rate with a reduced require-
ment for high-priority interrupt servicing. When new data is available in the SPI_TDR, the SPI
continues to transfer data. If the SPI_RDR (Receive Data Register) has not been read before
new data is received, the Overrun Error (OVRES) flag is set.
Note:
The programmable delay between the activation of the chip select and the start of the data
transfer (DLYBS), as well as the delay between each data transfer (DLYBCT), can be pro-
grammed for each of the four external chip selects. All data transfer characteristics, including
the two timing values, are programmed in registers SPI_CSR0 to SPI_CSR3 (Chip Select
Registers).
In Master Mode, the peripheral selection can be defined in two different ways:
•
•
Figure 77 and Figure 78 show the operation of the SPI in Master Mode. For details concerning
the flag and control bits in these diagrams, see the tables in the Programmer’s Model, starting
in Section .
This mode is used for transferring memory blocks without the extra overhead in the transmit
data register to determine the peripheral.
Fixed Peripheral Select is activated by setting bit PS to zero in SPI_MR (Mode Register). The
peripheral is defined by the PCS field in SPI_MR.
This option is only available when the SPI is programmed in Master Mode.
Variable Peripheral Select is activated by setting bit PS to one. The PCS field in SPI_TDR is
used to select the destination peripheral. The data transfer characteristics are changed when
the selected peripheral changes, according to the associated chip select register.
The PCS field in the SPI_MR has no effect.
This option is only available when the SPI is programmed in Master Mode.
Fixed Peripheral Select: SPI exchanges data with only one peripheral
Variable Peripheral Select: Data can be exchanged with more than one peripheral
As long as this flag is set, no data is loaded in the SPI_RDR. The user has to read the status
register to clear it.
1790A–ATARM–11/03
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