ATMEGA8L ATMEL [ATMEL Corporation], ATMEGA8L Datasheet - Page 115

• Manufacturer Part Number: ATMEGA8L
• Description: 8-bit AVR with 8K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

8-bit Timer/Counter
Register Description
Timer/Counter Control
Register – TCCR2
2486M–AVR–12/03
• Bit 7 – FOC2: Force Output Compare
The FOC2 bit is only active when the WGM bits specify a non-PWM mode. However, for
ensuring compatibility with future devices, this bit must be set to zero when TCCR2 is
written when operating in PWM mode. When writing a logical one to the FOC2 bit, an
immediate Compare Match is forced on the waveform generation unit. The OC2 output
is changed according to its COM21:0 bits setting. Note that the FOC2 bit is implemented
as a strobe. Therefore it is the value present in the COM21:0 bits that determines the
effect of the forced compare.
A FOC2 strobe will not generate any interrupt, nor will it clear the timer in CTC mode
using OCR2 as TOP.
The FOC2 bit is always read as zero.
• Bit 6,3 – WGM21:0: Waveform Generation Mode
These bits control the counting sequence of the counter, the source for the maximum
(TOP) counter value, and what type of waveform generation to be used. Modes of oper-
ation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare
Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See Table
42 and “Modes of Operation” on page 108.
Table 42. Waveform Generation Mode Bit Description
Note:
• Bit 5:4 – COM21:0: Compare Match Output Mode
These bits control the Output Compare Pin (OC2) behavior. If one or both of the
COM21:0 bits are set, the OC2 output overrides the normal port functionality of the I/O
pin it is connected to. However, note that the Data Direction Register (DDR) bit corre-
sponding to OC2 pin must be set in order to enable the output driver.
When OC2 is connected to the pin, the function of the COM21:0 bits depends on the
WGM21:0 bit setting. Table 43 shows the COM21:0 bit functionality when the WGM21:0
bits are set to a normal or CTC mode (non-PWM).
Bit
Read/Write
Initial Value
Mode
0
1
2
3
1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 def-
WGM21
(CTC2)
initions. However, the functionality and location of these bits are compatible with
previous versions of the timer.
0
0
1
1
FOC2
W
7
0
WGM20
(PWM2)
WGM20
R/W
0
1
0
1
6
0
COM21
Timer/Counter Mode
of Operation
Normal
PWM, Phase Correct
CTC
Fast PWM
R/W
5
0
COM20
R/W
4
0
(1)
WGM21
R/W
3
0
TOP
0xFF
0xFF
OCR2
0xFF
CS22
R/W
2
0
Update of
OCR2
Immediate
TOP
Immediate
TOP
CS21
ATmega8(L)
R/W
1
0
CS20
R/W
0
0
TOV2 Flag
Set
MAX
BOTTOM
MAX
MAX
TCCR2
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