ATMEGA8L ATMEL [ATMEL Corporation], ATMEGA8L Datasheet - Page 164

• Manufacturer Part Number: ATMEGA8L
• Description: 8-bit AVR with 8K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

Multi-master Bus
Systems, Arbitration and
Synchronization
164
ATmega8(L)
The TWI protocol allows bus systems with several masters. Special concerns have
been taken in order to ensure that transmissions will proceed as normal, even if two or
more masters initiate a transmission at the same time. Two problems arise in multi-mas-
ter systems:
•
•
The wired-ANDing of the bus lines is used to solve both these problems. The serial
clocks from all masters will be wired-ANDed, yielding a combined clock with a high
period equal to the one from the Master with the shortest high period. The low period of
the combined clock is equal to the low period of the Master with the longest low period.
Note that all masters listen to the SCL line, effectively starting to count their SCL high
and low time-out periods when the combined SCL line goes high or low, respectively.
Figure 74. SCL Synchronization Between Multiple Masters
Arbitration is carried out by all masters continuously monitoring the SDA line after out-
putting data. If the value read from the SDA line does not match the value the Master
had output, it has lost the arbitration. Note that a Master can only lose arbitration when it
outputs a high SDA value while another Master outputs a low value. The losing Master
should immediately go to Slave mode, checking if it is being addressed by the winning
Master. The SDA line should be left high, but losing masters are allowed to generate a
clock signal until the end of the current data or address packet. Arbitration will continue
until only one Master remains, and this may take many bits. If several masters are trying
to address the same Slave, arbitration will continue into the data packet.
SCL from
SCL from
Master A
Master B
SCL Bus
An algorithm must be implemented allowing only one of the masters to complete the
transmission. All other masters should cease transmission when they discover that
they have lost the selection process. This selection process is called arbitration.
When a contending master discovers that it has lost the arbitration process, it
should immediately switch to Slave mode to check whether it is being addressed by
the winning master. The fact that multiple masters have started transmission at the
same time should not be detectable to the slaves, i.e. the data being transferred on
the bus must not be corrupted.
Different masters may use different SCL frequencies. A scheme must be devised to
synchronize the serial clocks from all masters, in order to let the transmission
proceed in a lockstep fashion. This will facilitate the arbitration process.
Line
TA
Counting Low Period
low
Masters Start
TB
low
TA
Counting High Period
high
Masters Start
TB
high
2486M–AVR–12/03