ATMEGA8L ATMEL [ATMEL Corporation], ATMEGA8L Datasheet - Page 41

• Manufacturer Part Number: ATMEGA8L
• Description: 8-bit AVR with 8K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

Watchdog Timer
Watchdog Timer Control
Register – WDTCR
2486M–AVR–12/03
The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at
1 MHz. This is the typical value at V
at other V
interval can be adjusted as shown in Table 17 on page 42. The WDR – Watchdog Reset
– instruction resets the Watchdog Timer. The Watchdog Timer is also reset when it is
disabled and when a Chip Reset occurs. Eight different clock cycle periods can be
selected to determine the reset period. If the reset period expires without another
Watchdog Reset, the ATmega8 resets and executes from the Reset Vector. For timing
details on the Watchdog Reset, refer to page 39.
To prevent unintentional disabling of the Watchdog, a special turn-off sequence must be
followed when the Watchdog is disabled. Refer to the description of the Watchdog Timer
Control Register for details.
Figure 20. Watchdog Timer
• Bits 7..5 – Res: Reserved Bits
These bits are reserved bits in the ATmega8 and will always read as zero.
• Bit 4 – WDCE: Watchdog Change Enable
This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog
will not be disabled. Once written to one, hardware will clear this bit after four clock
cycles. Refer to the description of the WDE bit for a Watchdog disable procedure. In
Safety Level 1 and 2, this bit must also be set when changing the prescaler bits. See the
Code Examples on page 43.
Bit
Read/Write
Initial Value
CC
levels. By controlling the Watchdog Timer prescaler, the Watchdog Reset
R
7
–
0
OSCILLATOR
WATCHDOG
R
6
–
0
R
5
–
0
CC
= 5V. See characterization data for typical values
WDCE
R/W
4
0
WDE
R/W
3
0
WDP2
R/W
2
0
WDP1
ATmega8(L)
R/W
1
0
WDP0
R/W
0
0
WDTCR
41