M306V0ME-107FP MITSUBISHI [Mitsubishi Electric Semiconductor], M306V0ME-107FP Datasheet - Page 153

• Manufacturer Part Number: M306V0ME-107FP
• Description: SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
• Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]

Rev. 1.0
Figure 2.14.6 V
2.14.2 Clamping Circuit and Low-pass Filter
2.14.3 Sync Slice Circuit
2.14.4 Synchronous Signal Separation Circuit
The clamp circuit clamps the sync chip part of the composite video signal input from the CV
pass filter attenuates the noise of clamped composite video signal. The CV
signal is input requires a capacitor (0.1 mF) coupling outside. Pull down the CV
hundreds of kiloohms to 1 M . In addition, we recommend to install externally a simple low-pass filter
using a resistor and a capacitor at the CV
This circuit takes out a composite sync signal from the output signal of the low-pass filter.
This circuit separates a horizontal synchronous signal and a vertical synchronous signal from the compos-
ite sync signal taken out in the sync slice circuit.
Figure 2.14.6 shows a V
reference clock which the timing generating circuit outputs.
Reading bit 5 of data slicer control register 2 permits determinating the shape of the V-pulse portion of the
composite sync signal. As shown in Figure 2.14.7, when the A level matches the B level, this bit is “0.” In
the case of a mismatch, the bit is “1.”
(1) Horizontal synchronous signal (H
(2) Vertical synchronous signal (V
A one-shot horizontal synchronizing signal Hsep is generated at the falling edge of the composite sync
signal.
As a Vsep signal generating method, it is possible to select one of the following 2 methods by using bit
4 of the data slicer control register 2 (address 0261
•Method 1 The “L” level width of the composite sync signal is measured. If this width exceeds a
•Method 2 The “L” level width of the composite sync signal is measured. If this width exceeds a
sep
certain time, a V
signal immediately after this “L” level.
certain time, it is detected whether a falling of the composite sync signal exits or not in the
“L” level period of the timing signal immediately after this “L” level. If a falling exists, a V
signal is generated in synchronization with the rising of the timing signal (refer to Figure
2.14.6).
generating timing (method 2)
sep
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
generating timing. The timing signal shown in the figure is generated from the
Composite
sync signal
Timing
signal
V
sep
A V
immediately after the “L” level width of the composite
sync signal exceeds a certain time.
signal
sep
sep
signal is generated at a rising of the timing signal
signal is generated in synchronization with the rising of the timing
sep
sep
)
IN
)
pin (refer to Figure 2.14.1).
Measure “L” period
16
).
and ON-SCREEN DISPLAY CONTROLLER
MITSUBISHI MICROCOMPUTERS
IN
M306V0ME-XXXFP
pin to which composite video
IN
pin with a resistor of
M306V0EEFP
IN
pin. The low-
sep
153