M306V0ME-107FP MITSUBISHI [Mitsubishi Electric Semiconductor], M306V0ME-107FP Datasheet - Page 39

• Manufacturer Part Number: M306V0ME-107FP
• Description: SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
• Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]

Rev. 1.0
The following paragraphs describes the clocks generated by the clock generating circuit.
(1) Main clock
(2) Sub-clock
(3) BCLK
(4) Peripheral function clock (f
(5) f
(6) f
The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by
8 to the BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 0006
Stopping the clock, after switching the operating clock source of CPU to the sub-clock, reduces the
power dissipation.
After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main
clock oscillation circuit can be reduced using the X
0007
tion. This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at
a reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before
stop mode is retained.
The sub-clock is generated by the sub clock oscillation circuit. No sub clock is generated after a reset.
After oscillation is started using the port Xc select bit (bit 4 at address 0006
selected as the BCLK by using the system clock select bit (bit 7 at address 0006
that the sub-clock oscillation has fully stabilized before switching.
After the oscillation of the sub-clock oscillation circuit has stabilized, the drive capacity of the sub-clock
oscillation circuit can be reduced using the X
0006
This bit changes to “1” when shifting to stop mode and at a reset.
The internal clock
clock by 1, 2, 4, 8, or 16. The BCLK is derived by dividing the main clock by 8 after a reset. The BCLK
signal can be output from pin BCLK by the BCLK output disable bit (bit 7 at address 0004
memory expansion and the microprocessor modes.
The main clock division select bit 0 (bit 6 at address 0006
speed/medium-speed to stop mode and at reset. When sifting from low-speed/low power dissipation
mode to stop mode, the value before stop mode is retained.
The clock for the peripheral devices is derived by dividing the main clock by 1, 8 or 32. The peripheral
function clock is stopped by stopping the main clock or by setting the WAIT peripheral function clock
stop bit (bit 2 at 0006
This clock is derived by dividing the sub-clock by 32. It is used for the timer A and timer B counts.
This clock has the same frequency as the sub-clock. It is used for the BCLK and for the watchdog
timer.
C32
C
16
16
). Reducing the drive capacity of the main clock oscillation circuit reduces the power dissipa-
). Reducing the drive capacity of the sub-clock oscillation circuit reduces the power dissipation.
is the clock that drives the CPU, and is fc or the clock derived by dividing the main
16
) to “1” and then executing a WAIT instruction.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
1,
f
8,
f
32,
f
1SIO2
, f
CIN
8SIO2
-X
IN
COUT
, f
-X
32SIO2,
OUT
16
drive capacity select bit (bit 3 at address
drive capacity select bit (bit 5 at address
) changes to “1” when shifting from high-
f
AD
and ON-SCREEN DISPLAY CONTROLLER
)
MITSUBISHI MICROCOMPUTERS
M306V0ME-XXXFP
16
), the sub-clock can be
16
M306V0EEFP
). However, be sure
16
) in the
16
).
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