M306V0ME-107FP MITSUBISHI [Mitsubishi Electric Semiconductor], M306V0ME-107FP Datasheet - Page 49

• Manufacturer Part Number: M306V0ME-107FP
• Description: SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
• Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]

Rev. 1.0
2.7.3 Hardware Interrupts
Hardware interrupts are classified into two types — special interrupts and peripheral I/O interrupts.
(1) Special interrupts
(2) Peripheral I/O interrupts
Special interrupts are non-maskable interrupts.
• Reset
• DBC interrupt
• Watchdog timer interrupt
• Single-step interrupt
• Address match interrupt
A peripheral I/O interrupt is generated by one of built-in peripheral functions. Built-in peripheral func-
tions are dependent on classes of products, so the interrupt factors too are dependent on classes of
products. The interrupt vector table is the same as the one for software interrupt numbers 0 through
31 the INI instruction uses. Peripheral I/O interrupts are maskable interrupts.
• Bus collision detection interrupt
• DMA0 interrupt, DMA1 interrupt
• V
• A-D conversion interrupt
• UART0 transmission, UART2 transmission/NACK interrupts
• UART0 reception, UART2 reception/ACK interrupts
• Timer A0 interrupt through timer A4 interrupt
• Timer B0 interrupt through timer B2 interrupt
• INT0 interrupt and INT1 interrupt
Reset occurs if an “L” is input to the RESET pin.
________
This interrupt is exclusively for the debugger, do not use it in other circumstances.
Generated by the watchdog timer.
This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug
flag (D flag) set to “1,” a single-step interrupt occurs after one instruction is executed.
An address match interrupt occurs immediately before the instruction held in the address indicated
by the address match interrupt register is executed with the address match interrupt enable bit set to
“1.” If an address other than the first address of the instruction in the address match interrupt register
is set, no address match interrupt occurs. For address match interrupt, see 2.11 Address match
Interrupt.
This is an interrupt that the serial I/O bus collision detection generates.
These are interrupts DMA generates.
V
This is an interrupt that the A-D converter generates.
These are interrupts that the serial I/O transmission generates.
These are interrupts that the serial I/O reception generates.
These are interrupts that timer A generates
These are interrupts that timer B generates.
________
An INT interrupt occurs if either a rising edge or a falling edge or a both edge is input to the INT pin.
SYNC
SYNC
______
interrupt occurs if a V
interrupt
________
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
SYNC
edge is input.
____________
and ON-SCREEN DISPLAY CONTROLLER
MITSUBISHI MICROCOMPUTERS
M306V0ME-XXXFP
M306V0EEFP
______
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