M306V0ME-107FP MITSUBISHI [Mitsubishi Electric Semiconductor], M306V0ME-107FP Datasheet - Page 17

• Manufacturer Part Number: M306V0ME-107FP
• Description: SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
• Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]

Rev. 1.0
Figure 2.2.2 Flag register (FLG)
The C, Z, S, and O flags are changed when instructions are executed. See the software manual for
details.
• Bit 5: Overflow flag (O flag)
• Bit 6: Interrupt enable flag (I flag)
• Bit 7: Stack pointer select flag (U flag)
• Bits 8 to 11: Reserved area
• Bits 12 to 14: Processor interrupt priority level (IPL)
• Bit 15: Reserved area
This flag is set to “1” when an arithmetic operation resulted in overflow; otherwise, cleared to “0”.
This flag enables a maskable interrupt.
An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared to
“0” when the interrupt is acknowledged.
Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected
when this flag is “1”.
This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of software
interrupt Nos. 0 to 31 is executed.
Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight
processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt
is enabled.
b15
IPL
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
U
I
O
B
S
Z
D
C
b0
and ON-SCREEN DISPLAY CONTROLLER
Flag register (FLG)
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt prior
Reserved area
MITSUBISHI MICROCOMPUTERS
M306V0ME-XXXFP
M306V0EEFP
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