S9S08AW16A FREESCALE [Freescale Semiconductor, Inc], S9S08AW16A Datasheet - Page 295

no-image

S9S08AW16A

Manufacturer Part Number
S9S08AW16A
Description
HCS08 Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
S9S08AW16AE0CFT
Manufacturer:
FREESCALE
Quantity:
20 000
Part Number:
S9S08AW16AE0CLC
Manufacturer:
FREESCALE
Quantity:
20 000
Part Number:
S9S08AW16AE0CLD
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
S9S08AW16AE0CLDR
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Part Number:
S9S08AW16AE0MLC
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
S9S08AW16AE0MLD
Manufacturer:
Freescal
Quantity:
12
Part Number:
S9S08AW16AE0MLD
Manufacturer:
FREESCALE
Quantity:
18 240
Part Number:
S9S08AW16AE0MLD
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
S9S08AW16AE0MLD
Manufacturer:
FREESCALE
Quantity:
18 240
The average chip-junction temperature (T
where:
For most applications, P
(if P
Solving equations 1 and 2 for K gives:
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring
P
solving equations 1 and 2 iteratively for any value of T
A.5
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early
CMOS circuits, normal handling precautions should be used to avoid exposure to static discharge.
Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels
of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade
Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body
Model (HBM), the Machine Model (MM) and the Charge Device Model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
Freescale Semiconductor
D
(at equilibrium) for a known T
I/O
is neglected) is:
ESD Protection and Latch-Up Immunity
T
θ
P
P
P
Model
JA
A
D
int
I/O
2
3
4
= Ambient temperature, °C
= P
= Package thermal resistance, junction-to-ambient, °C/W
= I
= Power dissipation on input and output pins — user determined
Junction to Ambient Natural Convection
1s - Single Layer Board, one signal layer
2s2p - Four Layer Board, 2 signal and 2 power layers
int
DD
+ P
× V
I/O
I/O
DD
<< P
, Watts — chip internal power
Table A-4. ESD and Latch-up Test Conditions
K = P
int
A
and can be neglected. An approximate relationship between P
MC9S08AC16 Series Data Sheet, Rev. 8
. Using this value of K, the values of P
D
P
T
× (T
Description
D
J
= K ÷ (T
= T
J
A
) in °C can be obtained from:
+ 273°C) + θ
A
+ (P
J
D
+ 273°C)
× θ
Appendix A Electrical Characteristics and Timing Specifications
A
JA
JA
.
)
× (P
D
)
2
Symbol
D
and T
Value
J
can be obtained by
Unit
D
Eqn. A-1
Eqn. A-2
Eqn. A-3
and T
295
J

Related parts for S9S08AW16A