S9S08AW16A FREESCALE [Freescale Semiconductor, Inc], S9S08AW16A Datasheet - Page 64

• Manufacturer Part Number: S9S08AW16A
• Description: HCS08 Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Chapter 5 Resets, Interrupts, and System Configuration
Each of these sources, with the exception of the background debug forced reset, has an associated bit in
the system reset status register.
5.4
The COP watchdog is intended to force a system reset when the application software fails to execute as
expected. To prevent a system reset from the COP timer (when it is enabled), application software must
reset the COP counter periodically. If the application program gets lost and fails to reset the COP counter
before it times out, a system reset is generated to force the system back to a known starting point.
After any reset, the COPE becomes set in SOPT enabling the COP watchdog (see
Options Register
it can be disabled by clearing COPE. The COP counter is reset by writing any value to the address of SRS.
This write does not affect the data in the read-only SRS. Instead, the act of writing to this address is
decoded and sends a reset signal to the COP counter.
The COPCLKS bit in SOPT2 (see
information) selects the clock source used for the COP timer. The clock source options are either the bus
clock or an internal 1-kHz clock source. With each clock source, there is an associated short and long
time-out controlled by COPT in SOPT.
COPT bits. The COP watchdog defaults to operation from the bus clock source and the associated long
time-out (2
Even if the application will use the reset default settings of COPE, COPCLKS, and COPT, the user must
write to the write-once SOPT and SOPT2 registers during reset initialization to lock in the settings. That
way, they cannot be changed accidentally if the application program gets lost. The initial writes to SOPT
and SOPT2 will reset the COP counter.
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Computer operating properly (COP) timer
Illegal opcode detect
Illegal address detect
Background debug forced reset
The reset pin (RESET)
Clock generator loss of lock and loss of clock reset
Computer Operating Properly (COP) Watchdog
18
cycles).
1
Values are shown in this column based on t
Section A.10.1, “Control
(SOPT),” for additional information). If the COP watchdog is not used in an application,
COPCLKS
0
0
1
1
Control Bits
Table 5-1. COP Configuration Options
Section 5.9.10, “System Options Register 2
MC9S08AC16 Series Data Sheet, Rev. 8
COPT
Timing,” for the tolerance of this value.
0
1
0
1
Table 5-1
Clock Source
summaries the control functions of the COPCLKS and
~1 kHz
~1 kHz
RTI
Bus
Bus
= 1 ms. See t
RTI
COP Overflow Count
2
2
8
in the appendix
5
cycles (256 ms)
cycles (32 ms)
2
2
13
18
cycles
cycles
(SOPT2),” for additional
Section 5.9.4, “System
1
1
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