S9S08AW16A FREESCALE [Freescale Semiconductor, Inc], S9S08AW16A Datasheet - Page 39

• Manufacturer Part Number: S9S08AW16A
• Description: HCS08 Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

3.6.4
The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below
the LVD voltage. If the LVD is enabled in stop by setting the LVDE and the LVDSE bits, then the voltage
regulator remains active during stop mode. If the user attempts to enter stop2 with the LVD enabled for
stop, the MCU will instead enter stop3.
LVD is enabled.
3.6.5
When the MCU enters any stop mode, system clocks to the internal peripheral modules are stopped. Even
in the exception case (ENBDM = 1), where clocks are kept alive to the background debug logic, clocks to
the peripheral systems are halted to reduce power consumption. Refer to
specific information on system behavior in stop modes.
I/O Pins
Memory
ICG — In stop3 mode, the ICG enters its low-power standby state. The oscillator may be kept running
when the ICG is in standby by setting OSCSTEN. In stop2 mode, the ICG is turned off. The oscillator
cannot be kept running in stop2 even if OSCSTEN is set. If the MCU is configured to go into stop2 mode,
the ICG will be reset upon wake-up from stop and must be reinitialized.
Freescale Semiconductor
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Mode
Stop3
Mode
Stop3
All I/O pin states remain unchanged when the MCU enters stop3 mode.
If the MCU is configured to go into stop2 mode, all I/O pins states are latched before entering stop.
All RAM and register contents are preserved while the MCU is in stop3 mode.
All registers will be reset upon wake-up from stop2, but the contents of RAM are preserved and
pin states remain latched until the PPDACK bit is written. The user may save any memory-mapped
register data into RAM before entering stop2 and restore the data upon exit from stop2.
The contents of the FLASH memory are non-volatile and are preserved in any of the stop modes.
LVD Enabled in Stop Mode
On-Chip Peripheral Modules in Stop Modes
PPDC
PPDC
0
0
CPU, Digital
Peripherals,
CPU, Digital
Peripherals,
Standby
Standby
FLASH
FLASH
Table 3-2. BDM Enabled Stop Mode Behavior
Table 3-3. LVD Enabled Stop Mode Behavior
MC9S08AC16 Series Data Sheet, Rev. 8
Standby
Standby
RAM
RAM
Table 3-3
Active
ICG
ICG
Off
summarizes the behavior of the MCU in stop when the
Optionally on
Optionally on
ADC
ADC
Regulator
Regulator
Active
Active
Section 3.6.2, “Stop3
States held Optionally on
States held Optionally on
I/O Pins
I/O Pins
Chapter 3 Modes of Operation
RTI
RTI
Mode” for
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