S9S08AW16A FREESCALE [Freescale Semiconductor, Inc], S9S08AW16A Datasheet - Page 72

• Manufacturer Part Number: S9S08AW16A
• Description: HCS08 Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Chapter 5 Resets, Interrupts, and System Configuration
5.9.2
This register includes seven read-only status flags to indicate the source of the most recent reset. When a
debug host forces reset by writing 1 to BDFR in the SBDFR register, none of the status bits in SRS will
be set. Writing any value to this register address clears the COP watchdog timer without affecting the
contents of this register. The reset state of these bits depends on what caused the MCU to reset.
72
Any other
reset:
POR
LVR:
Field
ILOP
POR
COP
PIN
7
6
5
4
W
R
U = Unaffected by reset
1
Any of these reset sources that are active at the time of reset will cause the corresponding bit(s) to be set; bits
corresponding to sources that are not active at the time of reset will be cleared.
System Reset Status Register (SRS)
POR
Power-On Reset — Reset was caused by the power-on detection logic. Because the internal supply voltage was
ramping up at the time, the low-voltage reset (LVR) status bit is also set to indicate that the reset occurred while
the internal supply was below the LVR threshold.
0 Reset not caused by POR.
1 POR caused reset.
External Reset Pin — Reset was caused by an active-low level on the external reset pin.
0 Reset not caused by external reset pin.
1 Reset came from external reset pin.
Computer Operating Properly (COP) Watchdog — Reset was caused by the COP watchdog timer timing out.
This reset source may be blocked by COPE = 0.
0 Reset not caused by COP timeout.
1 Reset caused by COP timeout.
Illegal Opcode — Reset was caused by an attempt to execute an unimplemented or illegal opcode. The STOP
instruction is considered illegal if stop is disabled by STOPE = 0 in the SOPT register. The BGND instruction is
considered illegal if active background mode is disabled by ENBDM = 0 in the BDCSC register.
0 Reset not caused by an illegal opcode.
1 Reset caused by an illegal opcode.
U
1
0
7
Note
PIN
0
0
6
1
Writing any value to SRS address clears COP watchdog timer.
Table 5-4. SRS Register Field Descriptions
Figure 5-3. System Reset Status (SRS)
MC9S08AC16 Series Data Sheet, Rev. 8
Note
COP
0
0
5
1
Note
ILOP
0
0
4
1
Description
ILAD
3
0
0
0
Note
ICG
0
0
2
1
Freescale Semiconductor
LVD
1
1
0
1
0
0
0
0
0