FDC37B78X SMSC Corporation, FDC37B78X Datasheet - Page 130

• Manufacturer Part Number: FDC37B78X
• Description: Enhanced Super I/O Controller with ACPI Support/ Real Time Clock and Consumer IR
• Manufacturer: SMSC Corporation

KEYBOARD ISA INTERFACE
The FDC37B78x ISA interface is functionally
compatible with the 8042-style host interface. It
consists of the D0-7 data bus; the nIOR, nIOW
Note 1:These registers consist of three separate 8 bit registers. Status, Data/Command Write and
Data Read.
Keyboard Data Write
This is an 8 bit write only register.
written, the C/D status bit of the status register
is cleared to zero and the IBF bit is set.
Keyboard Data Read
This is an 8 bit read only register. If enabled by
"ENABLE FLAGS", when read, the KIRQ output
is cleared and the OBF flag in the status register
is cleared.
AUXOBF1 must be cleared in software.
ISA ADDRESS
OUT DBB
0x60
0x64
8042 INSTRUCTION
If not enabled, the KIRQ and/or
nIOW
0
1
0
1
TABLE 57 - ISA I/O ADDRESS MAP
Set OBF, and, if enabled, the KIRQ output signal goes high
nIOR
Table 58 - Host Interface Flags
1
0
1
0
When
BLOCK
KDATA
KDATA
KDCTL
KDCTL
130
and the Status register, Input Data register, and
Output Data register. TABLE 57 shows how the
interface decodes the control signals.
addition to the above signals, the host interface
includes keyboard and mouse IRQs.
Keyboard Command Write
This is an 8 bit write only register.
written, the C/D status bit of the status register
is set to one and the IBF bit is set.
Keyboard Status Read
This is an 8 bit read only register. Refer to the
description of the Status Register for more
information.
CPU-to-Host Communication
The FDC37B78x CPU can write to the Output
Data register
this register automatically sets Bit 0 (OBF) in
the Status register. See Table 58.
Keyboard Data Write (C/D=0)
Keyboard Data Read
Keyboard Command Write (C/D=1)
Keyboard Status Read
FLAG
FUNCTION (NOTE 1)
via
register DBB. A write to
When
In