FDC37B78X SMSC Corporation, FDC37B78X Datasheet - Page 196
FDC37B78X
Manufacturer Part Number
FDC37B78X
Description
Enhanced Super I/O Controller with ACPI Support/ Real Time Clock and Consumer IR
Manufacturer
SMSC Corporation
Datasheet
1.FDC37B78X.pdf
(258 pages)
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Soft Power Enable
Register 2
Default = 0x80
on Vbat POR
NAME
0xB1 R/W
INDEX
REG
The following bits are the enables for the wake-up
function of the nPowerOn bit. When enabled,
these bits allow their corresponding function to
turn on power to the system.
1 = ENABLED
0 = DISABLED
Bit[0] SP_RXD1: UART 1 Receive Data Pin
Bit[1] SP_RXD2: UART 2 Receive Data Pin
Bit[2] Reserved
Bit[3] RING Enable bit “RING_EN”
0=Disable.
1=Enable ring indicator on nRING pin as wakeup
function to activate nPowerOn.
Bit[4] Reserved
Bit[5] CIR Enable bit “CIR_EN”
0=Disable.
1=Enable CIR wakeup event to activate nPowerOn
Bit[6] Reserved
Bit[7] OFF_EN: After power up, this bit defaults to
1, i.e., enabled. This bit allows the software to
enable or disable the button control of power off.
196
DEFINITION
STATE
C
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