FDC37B78X SMSC Corporation, FDC37B78X Datasheet - Page 201
![no-image](/images/no-image-200.jpg)
FDC37B78X
Manufacturer Part Number
FDC37B78X
Description
Enhanced Super I/O Controller with ACPI Support/ Real Time Clock and Consumer IR
Manufacturer
SMSC Corporation
Datasheet
1.FDC37B78X.pdf
(258 pages)
- Current page: 201 of 258
- Download datasheet (2Mb)
Forced Disk
Change
Default = 0x03
on VTR POR
Floppy Data Rate
Select Shadow
UART1 FIFO
Control Shadow
NAME
0xC1 R/W
0xC2 R
0xC3 R
INDEX
REG
Force Change 1 and Force Change 0 can be
written to 1 are not clearable by software.
Force Change 1 is cleared on (nSTEP AND nDS1)
Force Change 0 is cleared on (nSTEP AND
nDS0).
DSK CHG (Floppy DIR Register, Bit 7) = (nDS0
AND Force Change 0) OR (nDS1 AND Force
Change 1) OR nDSKCHG.
Setting either of the Force Disk Change bits active
(1) forces the FDD nDSKCHG input active when
the appropriate drive has been selected.
Bit[0] Force Change for FDC0
0=Inactive
1=Active
Bit[1] Force Change for FDC1
0=Inactive
1=Active
Bit[2:7] Reserved, Reads 0
Floppy Data Rate Select Shadow Register
Bit[7] Soft Reset
Bit[6] Power Down
Bit[5] Reserved
Bit[4] PRECOMP 2
Bit[3] PRECOMP 1
Bit[2] PRECOMP 0
Bit[1] Data Rate Select 1
Bit[0] Data Rate Select 0
UART1 FIFO Control Shadow Register
Bit[7] RCVR Trigger MSB
Bit[6] RCVR Trigger LSB
Bit[5] Reserved
Bit[4] Reserved
Bit[3] DMA Mode Select
Bit[2] XMIT FIFO Reset
Bit[1] RCVR FIFO Reset
Bit[0] FIFO Enable
201
DEFINITION
STATE
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