FDC37B78X SMSC Corporation, FDC37B78X Datasheet - Page 139
FDC37B78X
Manufacturer Part Number
FDC37B78X
Description
Enhanced Super I/O Controller with ACPI Support/ Real Time Clock and Consumer IR
Manufacturer
SMSC Corporation
Datasheet
1.FDC37B78X.pdf
(258 pages)
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When RESET_DRV is active and the battery
voltage is below 1-volt nominal, the following
occurs:
1.
2.
RTC Interrupt
The interrupt generated by the RTC is an active
high output. The RTC interrupt output remains
high as long as the
interrupt is present and the corresponding
interrupt-enable
All 14 bytes are directly writable and readable by the host with the following exceptions:
a.
b.
c.
Registers 00-0D are initialized to 00h.
Access to all registers from the host are
blocked.
Register C is read only
Bit 7 of Register A and Bit 7 of Register D are read only
Bit 0 of Register B is read only
ADDRESS
0E-7Ch
7Dh
7Eh
7Fh
A
B
C
D
0
1
2
3
4
5
6
7
8
9
bit
is
REGISTER TYPE
status bit causing the
Table 62 - Real Time Clock Address Map, Bank 0
set.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Activating
Register 0: Seconds
Register 1: Seconds Alarm
Register 2: Minutes
Register 3: Minutes Alarm
Register 4: Hours
Register 5: Hours Alarm
Register 6: Day of Week
Register 7: Date of Month
Register 8: Month
Register 9: Year
Register A:
Register B: (Bit 0 is Read Only)
Register C:
Register D:VRT and Day of Month Alarm
Register E-7C: General Purpose
Register 7D: Century Byte
Register 7E: Control Register 1
Register 7F:General Purpose
139
RESET_DRV or reading register C clears the
RTC interrupt.
The
programming the RTC Primary Interrupt Select
to a non-zero value. If IRQ 8 is selected then
the
programmable through a bit in the OSC Global
Configuration Register.
Internal Registers
Table 62 shows the address map for bank 0 of
the RTC; time, calendar, alarm, control, status
bytes and 114 bytes of "CMOS" registers.
polarity
RTC
REGISTER FUNCTION
Interrupt
of
this
is
IRQ
brought
8
output
out
by
is
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