FDC37B78X SMSC Corporation, FDC37B78X Datasheet - Page 88

• Manufacturer Part Number: FDC37B78X
• Description: Enhanced Super I/O Controller with ACPI Support/ Real Time Clock and Consumer IR
• Manufacturer: SMSC Corporation

This chip incorporates an IBM XT/AT compatible
parallel port. This supports the optional PS/2
type bi-directional parallel port (SPP), the
Enhanced Parallel Port (EPP) and the Extended
Capabilities Port (ECP) parallel port modes.
Refer
information on disabling, power down, changing
the base address of the parallel port, and
selecting the mode of operation.
This chip also provides a mode for support of
the floppy disk controller on the parallel port.
The parallel port also incorporates SMSC's
ChiProtect circuitry, which prevents possible
damage to the parallel port due to printer power-
up.
Note 1: These registers are available in all modes.
Note 2: These registers are only available in EPP mode.
Note 3: For EPP mode, IOCHRDY must be connected to the ISA bus.
DATA PORT
STATUS
PORT
CONTROL
PORT
EPP ADDR
PORT
EPP DATA
PORT 0
EPP DATA
PORT 1
EPP DATA
PORT 2
EPP DATA
PORT 3
to
the
STROBE
TMOUT
Configuration
PD0
PD0
PD0
PD0
PD0
PD0
D0
AUTOFD
PD1
PD1
PD1
PD1
PD1
PD1
D1
0
Registers
nINIT
PD2
PD2
PD2
PD2
PD2
PD2
D2
0
PARALLEL PORT
for
nERR
PD3
SLC
PD3
PD3
PD3
PD3
PD3
D3
88
The functionality of the Parallel Port is achieved
through the use of eight addressable ports, with
their associated registers and control gating.
The control and data port are read/write by the
CPU, the status port is read/write in the EPP
mode. The address map of the Parallel Port is
shown below:
DATA PORT
STATUS PORT
CONTROL PORT
EPP ADDR PORT
EPP DATA PORT 0
EPP DATA PORT 1
EPP DATA PORT 2
EPP DATA PORT 3
The bit map of these registers is:
SLCT
IRQE
PD4
PD4
PD4
PD4
PD4
PD4
D4
PCD
PD5
PD5
PD5
PD5
PD5
PD5
D5
PE
nACK
PD6
PD6
PD6
PD6
PD6
PD6
BASE ADDRESS + 00H
BASE ADDRESS + 01H
BASE ADDRESS + 02H
BASE ADDRESS + 03H
BASE ADDRESS + 04H
BASE ADDRESS + 05H
BASE ADDRESS + 06H
BASE ADDRESS + 07H
D6
0
nBUSY
PD7
AD7
PD7
PD7
PD7
PD7
D7
0
Note
2,3
2,3
2,3
2,3
2,3
1
1
1