SB82371 Intel Corporation, SB82371 Datasheet - Page 10
SB82371
Manufacturer Part Number
SB82371
Description
82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR
Manufacturer
Intel Corporation
Datasheet
1.SB82371.pdf
(122 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SB82371SB
Manufacturer:
NSC
Quantity:
1 150
Company:
Part Number:
SB82371SB
Manufacturer:
INTEL
Quantity:
140
Part Number:
SB82371SB
Manufacturer:
INTEL
Quantity:
20 000
Part Number:
SB82371SB (SU093)
Manufacturer:
INTEL
Quantity:
20 000
82371FB (PIIX) AND 82371SB (PIIX3)
1.2.
10
PHOLD#
PHLDA#
Signal Name
TRDY#
IRDY#
STOP#
IDSEL
DEVSEL#
PAR
SERR#
MDRQ[1:0]
(PIIX Only)
MDAK[1:0]#
(PIIX Only)
Signal Name
Motherboard I/O Device Interface Signals
O
I
I/O
(s/t/s)
I/O
(s/t/s)
I/O
(s/t/s)
I
I/O
(s/t/s)
O
I
Type
I
O
Type
PCI HOLD: The PIIX/PIIX3 asserts this signal to request the PCI Bus.
The PIIX3 implements the passive release mechanism by toggling PHOLD#
inactive for one PCICLK.
PCI HOLD ACKNOWLEDGE: This signal is asserted to grant the PCI bus
to the PIIX/PIIX3.
TARGET READY: Asserted when the target is ready for a data transfer.
INITIATOR READY: Asserted when the initiator is ready for a data
transfer.
STOP: Asserted by the target to request the master to stop the current
transaction.
INITIALIZATION DEVICE SELECT: IDSEL is used as a chip select during
configuration read and write transactions.
DEVICE SELECT: The PIIX/PIIX3 asserts DEVSEL# to claim a PCI
transaction through positive or subtractive decoding.
CALCULATED PARITY SIGNAL: PAR is "even" parity and is calculated
on 36 bits—AD[31:0] plus C/BE[3:0]#.
SYSTEM ERROR: SERR# can be pulsed active by any PCI device that
detects a system error condition. Upon sampling SERR# active, the
PIIX/PIIX3 can be programmed to generate a non-maskable interrupt
(NMI) to the CPU.
MOTHERBOARD DEVICE DMA REQUEST: These signals can be
connected internally to any of DREQ[3:0,7:5]. Each pair of request/
acknowledge signals is controlled by a separate register. Each signal
can be configured as steerable interrupts for motherboard devices.
MOTHERBOARD DEVICE DMA ACKNOWLEDGE: These signals
can be connected internally to any of DACK[3:0,7:5]. Each pair of
request/ acknowledge signals is controlled by a separate register.
Each signal can be configured as steerable interrupts for motherboard
devices.
Description
Description