SB82371 Intel Corporation, SB82371 Datasheet - Page 33

• Manufacturer Part Number: SB82371
• Description: 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR
• Manufacturer: Intel Corporation

2.2.5.
Address Offset:
Default Value:
Attribute:
This 8 bit register contains device stepping information. Writes to this register have no effect.
2.2.6.
Address Offset:
Default Value:
Attribute:
This register contains the device programming interface information related to the Sub-Class Code and Base
Class Code definition for the PIIX3 (function 0). This register also identifies the Base Class Code and the
function sub-class in relation to the Base Class Code.
2.2.7.
Address Offset:
Default Value:
Attribute:
The HEDT Register identifies the PIIX/PIIX3 as a multi-function device.
2.2.8.
Address Offset:
Default Value:
Attribute:
The I/O recovery mechanism in the PIIX/PIIX3 is used to add additional recovery delay between CPU or PCI
master originated 8-bit and 16-bit I/O cycles to the ISA Bus. The PIIX/PIIX3 automatically forces a minimum
delay of 3.5 SYSCLKs between back-to-back 8 and 16-bit I/O cycles to the ISA Bus. This delay is measured
from the rising edge of the I/O command (IOR# or IOW#) to the falling edge of the next I/O command. If a
delay of greater than 3.5 SYSCLKs is required, the ISA I/O Recovery Time Register can be programmed to
7:0
23:1
6
15:8
7:0
7:0
Bit
Bit
Bit
RID—REVISION IDENTIFICATION REGISTER (Function 0)
CLASSC CLASS CODE REGISTER (Function 0)
HEDT—HEADER TYPE REGISTER (Function 0)
IORT—ISA I/O RECOVERY TIMER REGISTER (Function 0)
Revision ID Byte. The register is hardwired to the default value.
Base Class Code (BASEC). 06h=Bridge device.
Sub-Class Code (SCC). 01h=PCI-to-ISA Bridge.
Programming Interface (PI). 00h=hardwired as a PCI-to-ISA Bridge.
Device Type (DEVICET). 80h=multi-function device.
08h
Refer to applicable specification update document
Read Only
09 0Bh
060100h
Read Only
0Eh
80h
Read Only
4Ch
4Dh
Read/Write
Description
Description
Description
82371FB (PIIX) AND 82371SB (PIIX3)
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