SB82371 Intel Corporation, SB82371 Datasheet - Page 97

• Manufacturer Part Number: SB82371
• Description: 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR
• Manufacturer: Intel Corporation

The Data Register is accessed as a 16-bit register for PIO transfers (except for ECC bytes). All other
registers are accessed as 8-bit quantities.
The PIIX/PIIX3 claims all accesses to these ranges. The byte enables do not have to be externally decoded
to assert DEVSEL#. Accesses to byte 3 of the Control Block are forwarded to ISA where the floppy disk
controller responds.
Each of the two drives (drive 0 or 1) on a cable implement separate ATA register files. To determine the
targeted drive, the PIIX/PIIX3 shadows the value of bit 4 (drive bit) of byte 6 (drive/head register) of the ATA
command block (CS1x#) for each of the two IDE connectors (primary and secondary).
3.5.2.
The PIIX/PIIX3 includes fast timing modes. The fast timing modes can be enabled only for the IDE data ports.
All other transactions to the IDE registers are run in single transaction mode with compatible timings.
Up to 2 IDE devices may be attached per IDE connector (drive 0 and drive 1). For each connector in a PIIX
system, only one fast timing mode may be specified (via the IDETIM Register). This mode can be applied to
drive 0, drive 1, or both. Transactions targeting the other drive will use compatible timing.
For the PIIX3, the IDETIM and SIDETIM Registers permit different timing modes to be programmed for drive
0 and drive 1 of the same connector.
00h
01h
02h
03h
04h
05h
06h
07h
00h
01h
02h
03h
IO Offset
IO Offset
ENHANCED TIMING MODES
Table 13. IDE Legacy I/O port definition: COMMAND BLOCK (CS1x# chip select)
Table 14. IDE Legacy I/O port definition: CONTROL BLOCK (CS3x# chip select)
Data
Error/Features
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive/Head
Status/Command
Reserved
Reserved
Alt Status/Device control
Forward to ISA (Floppy)
Register Function (Read / Write)
Register Function (Read / Write)
82371FB (PIIX) AND 82371SB (PIIX3)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
reserved
reserved
R/W
R/W
Access
Access
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