SB82371 Intel Corporation, SB82371 Datasheet - Page 71

• Manufacturer Part Number: SB82371
• Description: 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR
• Manufacturer: Intel Corporation

2.5.3.3.
I/O Address:
Default Value:
Attribute:
The meaning of ICW3 differs between CNTRL-1 and CNTRL-2. On CNTRL-1, the master controller, ICW3
indicates which CNTRL-1 IRQ line physically connects the INTR output of CNTRL-2 to CNTRL-1.
2.5.3.4.
I/O Address:
Default Value:
Attribute:
On CNTRL-2 (the slave controller), ICW3 is the slave identification code broadcast by CNTRL-1.
2.5.3.5.
I/O Address:
Default Value:
Attribute:
Both PIIX/PIIX3 interrupt controllers must have ICW4 programmed as part of their initialization sequence.
7:3
2
1:0
7:5
4
3
2
1
0
7:3
2:0
Bit
Bit
Bit
Reserved. Must be programmed to all 0s.
Cascaded Mode Enable. This bit must be programmed to 1 selecting cascade mode.
Reserved. Must be programmed to all 0s.
Reserved. Must be programmed to all 0s.
Slave Identification Code. Must be programmed to 010b.
Reserved. Must be programmed to all 0s.
Special Fully Nested Mode (SFNM). Bit 4, SFNM, should normally be disabled by writing a 0
to this bit. If SFNM=1, the special fully nested mode is programmed.
Buffered mode (BUF). Must be programmed to 0 selecting non-buffered mode.
Master/Slave in Buffered Mode. Should always be programmed to 0. Bit not used.
AEOI (Automatic End of Interrupt). This bit should normally be programmed to 0. This is the
normal end of interrupt. If this bit is 1, the automatic end of interrupt mode is programmed.
Microprocessor Mode. Must be programmed to 1 indicating an Intel Architecture-based
system.
ICW3—Initialization Command Word 3 Register
ICW3—Initialization Command Word 3 Register
ICW4—Initialization Command Word 4 Register
INT CNTRL-1—021h
All bits undefined
Write Only
INT CNTRL-2—0A1h
All bits undefined
Write Only
INT CNTRL-1—021h; INT CNTRL-2—0A1h
01h
Write Only
Description
Description
Description
82371FB (PIIX) AND 82371SB (PIIX3)
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