UPSD3233 STMicroelectronics, UPSD3233 Datasheet - Page 118
UPSD3233
Manufacturer Part Number
UPSD3233
Description
Flash Programmable System Devices with 8032 Microcontroller Core
Manufacturer
STMicroelectronics
Datasheet
1.UPSD3233.pdf
(175 pages)
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UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV
Page Register
The 8-bit Page Register increases the addressing
capability of the MCU Core by a factor of up to 256.
The contents of the register can also be read by
the MCU. The outputs of the Page Register
(PGR0-PGR7) are inputs to the DPLD decoder
and can be included in the Sector Select (FS0-
FS7, CSBOOT0-CSBOOT3), and SRAM Select
(RS0) equations.
Figure 57. Page Register
118/175
RESET
R/ W
D0 - D7
D0
D1
D2
D3
D4
D5
D6
D7
REGISTER
PAGE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
If memory paging is not needed, or if not all 8 page
register bits are needed for memory paging, then
these bits may be used in the CPLD for general
logic.
Figure 57 shows the Page Register. The eight flip-
flops in the register are connected to the internal
data bus D0-D7. The MCU can write to or read
from the Page Register. The Page Register can be
accessed at address location CSIOP + E0h.
PGR0
PGR1
PGR2
PGR3
PGR4
PGR5
PGR6
PGR7
DPLD
CPLD
AND
PLD
INTERNAL PSD MODULE
SELECTS
AND LOGIC
AI05799