UPSD3233 STMicroelectronics, UPSD3233 Datasheet - Page 121

• Manufacturer Part Number: UPSD3233
• Description: Flash Programmable System Devices with 8032 Microcontroller Core
• Manufacturer: STMicroelectronics

Decode PLD (DPLD)
The DPLD, shown in Figure 59, is used for decod-
ing the address for PSD MODULE and external
components. The DPLD can be used to generate
the following decode signals:
Figure 59. DPLD Logic Array
Note: 1. Port A inputs are not available in the 52-pin package
8 Sector Select (FS0-FS7) signals for the
primary Flash memory (three product terms
each)
MCELLAB.FB [7:0] (FEEDBACKS)
MCELLBC.FB [7:0] (FEEDBACKS)
PGR0 -PGR7
I /O PORTS (PORT A,B,C) 1
A [ 15:0 ] 2
PD [ 2:1 ]
PDN (APD OUTPUT)
PSEN, RD, WR, ALE 2
RESET
RD_BSY
2. Inputs from the MCU module
2
(INPUTS)
(20)
(16)
(8)
(8)
(8)
(2)
(1)
(4)
(1)
(1)
UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV
4 Sector Select (CSBOOT0-CSBOOT3) signals
for the secondary Flash memory (three product
terms each)
1 internal SRAM Select (RS0) signal (two
product terms)
1 internal CSIOP Select signal (selects the PSD
MODULE registers)
2 internal Peripheral Select signals (Peripheral
I/O Mode).
3
3
3
3
3
3
3
3
3
3
3
3
2
1
1
1
RS0
CSIOP
PSEL0
PSEL1
CSBOOT 0
CSBOOT 1
CSBOOT 2
CSBOOT 3
FS0
FS1
FS7
FS2
FS3
FS5
FS6
FS4
SRAM SELECT
PERIPHERAL I/O
MODE SELECT
I/O DECODER
SELECT
8 PRIMARY FLASH
MEMORY SECTOR
SELECTS
AI06601
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