UPSD3233 STMicroelectronics, UPSD3233 Datasheet - Page 62

• Manufacturer Part Number: UPSD3233
• Description: Flash Programmable System Devices with 8032 Microcontroller Core
• Manufacturer: STMicroelectronics

UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV
Table 44. Description of the SCON Bits
62/175
Bit
7
6
5
4
3
2
1
0
Symbol
REN
SM0
SM1
SM2
RB8
TB8
RI
TI
(SM1,SM0)=(0,0): Shift Register. Baud rate = f
(SM1,SM0)=(1,0): 8-bit UART. Baud rate = variable
(SM1,SM0)=(0,1): 8-bit UART. Baud rate = f
(SM1,SM0)=(1,1): 8-bit UART. Baud rate = variable
Enables the multiprocessor communication features in Mode 2 and 3. In Mode 2 or 3, if
SM2 is set to '1,' RI will not be activated if its received 8th data bit (RB8) is '0.' In Mode
1, if SM2=1, RI will not be activated if a valid Stop Bit was not received. In Mode 0, SM2
should be '0'
Enables serial reception. Set by software to enable reception. Clear by software to
disable reception
The 8th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as
desired
In Modes 2 and 3, this bit contains the 8th data bit that was received. In Mode 1, if
SM2=0, RB8 is the Snap Bit that was received. In Mode 0, RB8 is not used
Transmit Interrupt Flag. Set by hardware at the end of the 8th bit time in Mode 0, or at
the beginning of the Stop Bit in the other modes, in any serial transmission. Must be
cleared by software
Receive Interrupt Flag. Set by hardware at the end of the 8th bit time in Mode 0, or
halfway through the Stop Bit in the other modes, in any serial reception (except for
SM2). Must be cleared by software
Function
OSC
OSC
/64 or f
/12
OSC
/32