UPSD3233 STMicroelectronics, UPSD3233 Datasheet - Page 128

• Manufacturer Part Number: UPSD3233
• Description: Flash Programmable System Devices with 8032 Microcontroller Core
• Manufacturer: STMicroelectronics

UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV
Figure 64. Peripheral I/O Mode
Table 92. Port Operating Modes
Note: 1. Port A is not available in the 52-pin package.
Table 93. Port Operating Mode Settings
Note: 1. N/A = Not Applicable
Table 94. I/O Port Latched Address Output Assignments
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MCU I/O
PLD I/O
McellAB Outputs
McellBC Outputs
Additional Ext. CS Outputs
PLD Inputs
Address Out
Peripheral I/O
JTAG ISP
MCU I/O
PLD I/O
Address Out
(Port A,B)
Peripheral I/O
(Port A)
Address a3-a0
2. On pins PC2, PC3, PC4, and PC7 only.
3. JTAG pins (TMS, TCK, TDI, TDO) are dedicated pins.
2. The direction of the Port A,B,C, and D pins are controlled by the Direction Register ORed with the individual output enable product
Port A (PA3-PA0)
Mode
term (.oe) from the CPLD AND Array.
Port Mode
Declare pins only
Logic equations
Declare pins only
Logic equations
(PSEL0 & 1)
Defined in PSDsoft
RD
PSEL0
PSEL1
VM REGISTER BIT 7
WR
Yes
Yes
No
No
Yes
Yes (A7 – 0)
Yes
No
Address a7-a4
Port A (PA7-PA4)
Port A
(1)
PSEL
0
N/A
1
N/A
Control Register
Yes
Yes
Yes
No
Yes
Yes (A7 – 0)
No
No
Setting
Port B
Address a3-a0
(1)
DATA BUS
D0 - D7
Port B (PB3-PB0)
1 = output,
0 = input (Note 2)
(Note 2)
1 (Note 2)
N/A
Direction Register
Yes
No
Yes
No
Yes
No
No
Yes
Setting
(2)
(3)
Port C
(1)
PA0 - PA7
Address a7-a4
N/A
N/A
N/A
PIO Bit = 1
VM Register Setting
Port B (PB7-PB4)
Yes
No
No
Yes
Yes
No
No
No
Port D
AI02886
(1)