UPSD3233 STMicroelectronics, UPSD3233 Datasheet - Page 12

• Manufacturer Part Number: UPSD3233
• Description: Flash Programmable System Devices with 8032 Microcontroller Core
• Manufacturer: STMicroelectronics

UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV
SUMMARY DESCRIPTION
12/175
Dual bank Flash memories
– Concurrent operation, read from memory
– Large 128KByte or 256KByte main Flash
– Large 32KByte secondary Flash memory di-
– Secondary Flash memory is large enough for
Large SRAM with battery back-up option
– 8KByte SRAM for RTOS, high-level languag-
Programmable Decode PLD for flexible address
mapping of all memories
– Place individual Flash and SRAM sectors on
– Built-in page register breaks restrictive 8032
– Special register swaps Flash memory seg-
High-speed clock standard 8032 core (12-cycle)
– 40MHz operation at 5V, 24MHz at 3.3V
– 2 UARTs with independent baud rate, three
USB Interface (uPSD3234A-40 only)
– Supports USB 1.1 Slow Mode (1.5Mbit/s)
– Control endpoint 0 and interrupt endpoints 1
I
– Capable of master or slave operation
5 Pulse Width Modulator (PWM) channels
– Four 8-bit PWM units
– One 8-bit PWM unit with programmable peri-
2
C interface for peripheral connections
while erasing and writing the other. In-Appli-
cation Programming (IAP) for remote updates
memory for application code, operating sys-
tems, or bit maps for graphic user interfaces
vided in small sectors. Eliminate external EE-
PROM with software EEPROM emulation
sophisticated communication protocol (USB)
during IAP while continuing critical system
tasks
es, communication buffers, and stacks
any address boundary
limit of 64KByte address space
ments between 8032 “program” space and
“data” space for efficient In-Application Pro-
gramming
16-bit Timer/Counters and two External Inter-
rupts
and 2
od
4-channel, 8-bit Analog-to-Digital Converter
(ADC) with analog supply voltage (V
Standalone Display Data Channel (DDC)
– For use in monitor, projector, and TV applica-
– Compliant with VESA standards DDC1 and
– Eliminate external DDC PROM
Six I/O ports with up to 46 I/O pins
– Multifunction I/O: GPIO, DDC, I
– Eliminates need for external latches and logic
3000 gate PLD with 16 macrocells
– Create glue logic, state machines, delays,
– Eliminate external PALs, PLDs, and 74HCxx
– Simple PSDsoft Express software ...Free
Supervisor functions
– Generates reset upon low voltage or watch-
– RESET Input pin; Reset output via PLD
In-System Programming (ISP) via JTAG
– Program entire chip in 10 - 25 seconds with
– Allows efficient manufacturing, easy product
– Eliminate sockets and pre-programmed parts
– Program with FlashLINK
Content Security
– Programmable Security Bit blocks access of
Zero-Power Technology
– Memories and PLD automatically reach
Packages
– 52-pin TQFP
– 80-pin TQFP: allows access to 8032 address/
tions
DDC2B
PLD I/O, supervisor, and JTAG
etc.
dog time-out. Eliminate external supervisor
device
no involvement of 8032
testing, and Just-In-Time inventory
device programmers and readers
standby current between input changes
data/control signals for connecting to external
peripherals
TM
cable and any PC
REF
2
C, PWM,
)