UPSD3233 STMicroelectronics, UPSD3233 Datasheet - Page 126

• Manufacturer Part Number: UPSD3233
• Description: Flash Programmable System Devices with 8032 Microcontroller Core
• Manufacturer: STMicroelectronics

UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV
I/O PORTS (PSD MODULE)
There are four programmable I/O ports: Ports A, B,
C, and D in the PSD MODULE. Each of the ports
is eight bits except Port D, which is 3 bits. Each
port pin is individually user configurable, thus al-
lowing multiple functions per port. The ports are
configured using PSDsoft Express Configuration
or by the MCU writing to on-chip registers in the
CSIOP space. Port A is not available in the 52-pin
package.
The topics discussed in this section are:
General Port Architecture
The general architecture of the I/O Port block is
shown in Figure 63. Individual Port architectures
are shown in Figure 65 to Figure 68. In general,
once the purpose for a port pin has been defined,
Figure 63. General I/O Port Architecture
126/175
General Port architecture
Port operating modes
Port Configuration Registers (PCR)
Port Data Registers
Individual Port functionality.
ADDRESS
ALE
MACROCELL OUTPUTS
EXT CS
WR
ENABLE PRODUCT TERM ( .OE )
WR
WR
CONTROL REG.
CPLD - INPUT
DATA OUT
READ MUX
DIR REG.
D
D
G
D
D
REG.
P
D
B
Q
Q
Q
Q
DATA IN
DATA OUT
ADDRESS
that pin is no longer available for other purposes.
Exceptions are noted.
As shown in Figure 63, the ports contain an output
multiplexer whose select signals are driven by the
configuration bits in the Control Registers (Ports A
and B only) and PSDsoft Express Configuration.
Inputs to the multiplexer include the following:
The Port Data Buffer (PDB) is a tri-state buffer that
allows only one source at a time to be read. The
Port Data Buffer (PDB) is connected to the Internal
Data Bus for feedback and can be read by the
MCU. The Data Out and macrocell outputs, Direc-
tion and Control Registers, and port pin input are
all connected to the Port Data Buffer (PDB).
Output data from the Data Out register
Latched address outputs
CPLD macrocell output
External Chip Select (ECS1-ECS2) from the
CPLD.
OUTPUT
OUTPUT
SELECT
MUX
ENABLE OUT
MACROCELL
INPUT
PORT PIN
AI06604