DA82562EZ Intel, DA82562EZ Datasheet
DA82562EZ
Related parts for DA82562EZ
DA82562EZ Summary of contents
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... Restriction on Hazardous Substances (RoHS)-banned materials, is available at: ftp://download.intel.com/design/packtech/material_content_IC_Package.pdf#pagemode=bookmark In addition, this device has been tested and conforms to the same parametric specifications as previous versions of the device. For more information regarding lead-free products from Intel Corporation, contact your Intel Field Sales repre- sentative. Datasheet Diagnostic loopback mode ...
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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel's website at http://www.intel.com. ...
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... January 2005 Datasheet Networking Silicon — 82562EZ Description Initial release (Intel Secret) Update to Table 10 - Pin Assignments (Intel Secret) Added part number (Intel Confidential) Table 15- Pin assignments revised from Rev. 1.3 to Rev 2.0 Removed confidential status Updated signal names to match design guides and reference schematics. ...
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Contents 1.0 Introduction......................................................................................................................... 1 1.1 Overview ............................................................................................................... 1 1.2 Scope .................................................................................................................... 1 1.3 Features ................................................................................................................ 1 1.4 Reference Documents...........................................................................................2 2.0 82562EZ Architectural Overview........................................................................................ 3 3.0 82562EZ Signal Descriptions ............................................................................................. 5 3.1 Signal Type Definitions ......................................................................................... 5 3.2 Twisted Pair Ethernet ...
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Networking Silicon 5.3 Medium Dependent Interface Registers 16 through 31 ...................................... 21 5.3.1 Register 16: PHY Status and Control Register Bit Definitions .............. 21 5.3.2 Register 17: PHY Unit Special Control Bit Definitions ........................... 21 5.3.3 Register 18: ...
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Introduction 1.1 Overview The 82562EZ is a highly-integrated Platform LAN Connect device designed for 10 or 100 Mbps Ethernet systems based on the IEEE 10BASE-T and 100BASE-TX standards. The IEEE 802.3u standard for 100BASE-TX defines networking over ...
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... IEEE 802.3 Standard for Local and Metropolitan Area Networks, Institute of Electrical and Electronics Engineers • 82555 10/100 Mbps LAN Physical Layer Interface Datasheet, Intel Corporation • LAN Connect Interface Specification, Intel Corporation • 82562EZ(EX)/82551QM & 82540EM Combined Footprint LOM Design Guide, AP-434, Intel Corporation • ...
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Architectural Overview The 82562EZ is a highly integrated Platform LAN Connect device that combines a 10BASE-T and 100BASE-TX physical layer interfaces. The 82562EZ supports a single interface fully compliant with the IEEE 802.3 standard. Figure 1. 82562EZ Block ...
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Signal Descriptions 3.1 Signal Type Definitions Type Name I Input O Output I/O Input/Output Multi-level MLT analog I/O B Bias Digital Power DPS Supply Analog Power APS Supply 3.2 Twisted Pair Ethernet (TPE) Pins Pin Name Type TDP ...
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Networking Silicon 3.4 Clock Pins Pin Name Type 3.5 Platform LAN Connect Interface Pins Pin Name Type JCLK O JRSTSYNC I JTXD[2:0] I JRXD[2: Description Crystal Input Clock. X1 and X2 can ...
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LED Pins Pin Name Type LILED# O ACTLED# O SPDLED# O 3.7 Miscellaneous Control Pins Pin Name Type ADV10 I ISOL_TCK I ISOL_TI I ISOL_EXEC I TOUT O TESTEN I Datasheet Description Link Integrity LED. The LED is active ...
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Networking Silicon 3.8 Power and Ground Connections Pin Name Type VCC DPS VSS DPS 8 Description Digital 3.3 V Power. These pins should be connected to the main digital power supply. Digital Ground. These pins should be connected ...
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Physical Layer Interface Functionality The 82562EZ is designed to work in Data Terminating Equipment (DTE) mode only. It supports a direct glueless interface to all components that comply with the LAN Connect specification. The following figure shows how the ...
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Networking Silicon Symbol 5B Symbol Code 4.1.1.2 100BASE-TX Scrambler and MLT-3 Encoder ...
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The MLT-3 encoder receives the scrambled Non-Return to Zero (NRZ) data stream from the scrambler and encodes the stream into MLT-3 for presentation to the driver. MLT-3 is similar to NRZ1 coding, but three levels are output instead of two. ...
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Networking Silicon 4.1.2.3 MLT-3 Decoder, Descrambler, and Receive Digital Section The 82562EZ first decodes the MLT-3 data, and then the descrambler reproduces the 5B symbols originated in the transmitter. The descrambling is based on synchronization to the transmission ...
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Twisted Pair Ethernet (TPE) Receive Buffer and Filter In 10 Mbps mode, data is expected to be received on the receive differential pair after passing through isolation transformers. The filter is implemented inside the 82562EZ for supporting single ...
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Networking Silicon 4.4 Dynamic Reduced Power & Auto Plugging Detection The 82562EZ can be configured to support a dynamic reduced power mode. This mode reduces power consumption of the 82562EZ when LAN activity is not present. The reduced ...
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The 82562EZ can enter a reduced power state manually through bit 11 of register 0. This bit is ORed with the LAN Connect power down bit, which allows the 82562EZ to enter a reduced power state. Table 4. Register 0: ...
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Platform LAN Connect Registers The following subsections describe PHY registers that are accessible through the LAN Connect management frame protocol. Acronyms mentioned in the registers are defined as follows: SC: Self cleared. RO: Read only. RW: Read/Write. E: EEPROM ...
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Networking Silicon Bit(s) Name 10 Isolate 9 Restart Auto- Negotiation 8 Duplex Mode 7 Collision Test 6:0 Reserved 5.1.2 Register 1: Status Register Bit Definitions Bit(s) Name 15 Reserved 14 100BASE-TX Full-duplex 13 100 Mbps Half- duplex 12 ...
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Bit(s) Name 5 Auto-Negotiation Complete 4 Remote Fault 3 Auto-Negotiation Ability 2 Link Status 1 Jabber Detect 0 Extended Capa- bility 5.1.3 Register 2: PHY Identifier Register Bit Definitions Bit(s) Name 15:0 PHY ID (high byte) 5.1.4 Register 3: PHY ...
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Networking Silicon Bit(s) Name 4:0 Selector Field 5.1.6 Register 5: Auto-Negotiation Link Partner Ability Register Bit Definitions Bit(s) Name 15 Next Page 14 Acknowledge 13 Remote Fault 12:5 Technology Abil- ity Field 4:0 Selector Field 5.1.7 Register 6: ...
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Medium Dependent Interface Registers 16 through 31 5.3.1 Register 16: PHY Status and Control Register Bit Definitions Bit(s) Name 15:14 Reserved 13 Reduced Power Down Disable 12 Reserved 11 Receive De-Seri- alizer In-Sync Indication 10 100BASE-TX Power-Down 9 10BASE-T ...
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Networking Silicon Bit(s) Name 11 Valid Link 10 Symbol Error Enable 9 Carrier Sense Disable 8 Disable Dynamic Power-Down 7 Auto-Negotiation Loopback 6 MDI Tri-State 5 Force Polarity 4 Auto Polarity Dis- able 3 Squelch Disable 2 Extended ...
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Register 20: 100BASE-TX Receive Disconnect Counter Bit Definitions Bit(s) Name 15:0 Disconnect Event 5.3.6 Register 21: 100BASE-TX Receive Error Frame Counter Bit Definitions Bit(s) Name 15:0 Receive Error Frame 5.3.7 Register 22: Receive Symbol Error Counter Bit Definitions Bit(s) ...
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Networking Silicon 5.3.10 Register 25: 10BASE-T Transmit Jabber Detect Counter Bit Definitions Bit(s) Name 15:0 Jabber Detect Counter 5.3.11 Register 27: PHY Unit Special Control Bit Definitions Bit(s) Name 15:6 Reserved 5 Switch Probe Mapping 4 Reserved 3 ...
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Voltage and Temperature Specifications 6.1 Absolute Maximum Ratings Maximum ratings are listed below: Case Temperature under Bias . . . . . . . . . . . . . . . . . . . . . . ...
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Networking Silicon 6.2.2 LAN Connect Interface DC Specifications Table 8. LAN Connect Interface DC Specifications Symbol Parameter Input/Output V CCJ Supply Voltage V Input Low Voltage IL Input High V IH Voltage Input Leakage I IL Current Output ...
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Table 11. 10BASE-T Receiver Symbol Parameter Input Differential R ID10 Resistance Input Differential V Accept Peak IDA10 Voltage Input Differential V Reject Peak IDR10 Voltage Input Common V ICM10 Mode Voltage NOTES: 1. The input differential resistance is measured across ...
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Test Port Functionality The 82562EZ’s XOR Tree Test Access Port (TAP) is the access point for test data to and from the device. The port provides the ability to perform basic production level testing. 7.1 Asynchronous Test Mode ...
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Networking Silicon Table 14. XOR Tree Chain Order Chain Order XOR Tree Output TOUT The following pins are not included in the XOR Tree chain: X1, ISOL_TCK, ISOL_EXEC, ISOL_TI and TESTEN. 30 Chain 11 SPDLED# 12 LILED# Datasheet ...
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... Package Information The 82562EZ is a 196 Ball Grid Array (BGA) package. The package dimensions are shown in Figure 5. More information on Intel device packaging is available in the Intel Packaging Handbook, which is available from the Intel Developer website.. Figure 5. Dimension Diagram for the 196-pin BGA Note: No changes to existing soldering processes are needed for the 0 ...
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Networking Silicon 8.2 Pinout Information Note: The power (VCC) and ground (VSS) pins have not been finalized and are subject to change. Do not finalize a design with this information. Revised information will be published when the product ...
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Table 15. 82562EZ Pin Assignments Pin Pin Name Number C10 VSS C11 ACTLED# C12 VSSA C13 TDP C14 TDN VSS D5 VSS D6 ...
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Networking Silicon Figure 6. 82562EZ Pin Out Diagram (Thru-the-Top View VSS VCC VSS VCC ...